[PATCH] [RFC][10/17] MCJIT execution engine (rtld) support for tilegx

[Jiong WANG]

Support some necessary tilegx runtime relocation types.

Please review, thanks

---
Regards,
Jiong
Tilera Corporation.



http://llvm-reviews.chandlerc.com/D520

Files:
  lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
  lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h

Index: lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
===================================================================
--- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
@@ -560,6 +560,126 @@
   }
 }
 
+void RuntimeDyldELF::resolveTileGXRelocation(const SectionEntry &Section,
+                                             uint64_t Offset,
+                                             uint64_t Value,
+                                             uint32_t Type,
+                                             int64_t Addend) {
+  DEBUG(dbgs() << "resolveTileGXRelocation, LocalAddress: "
+	       << Section.Address + Offset
+               << " FinalAddress: "
+               << format("%p",Section.LoadAddress + Offset)
+               << " Value: " << format("%llx",Value)
+               << " Type: " << format("%x",Type)
+               << " Addend: " << format("%llx",Addend)
+               << "\n");
+
+  uint64_t* TargetPtr = (uint64_t*)(Section.Address + Offset);
+  Value += Addend;
+
+  switch(Type) {
+  default:
+    llvm_unreachable("Not implemented relocation type!");
+    break;
+  case ELF::R_TILEGX_64: {
+    *TargetPtr = Value;
+    break;
+  }
+  case ELF::R_TILEGX_32: {
+    uint32_t TruncatedValue = (Value & 0xFFFFFFFF);
+    *TargetPtr = TruncatedValue;
+    break;
+  }
+  case ELF::R_TILEGX_32_PCREL: {
+    uint64_t FinalAddress = Section.LoadAddress + Offset;
+    int64_t RealOffset = Value - FinalAddress;
+    assert(RealOffset <= INT32_MAX && RealOffset >= INT32_MIN);
+    int32_t TruncOffset = (RealOffset & 0xFFFFFFFF);
+    *TargetPtr = TruncOffset;
+    break;
+  }
+  // R_TILEGX_JUMPOFF_X1
+  //
+  //       the 64bit instruction bundle
+  //  ---------------------------------------------
+  // |     |                |                      |
+  // V     V                V                      V
+  // 63    57              31                      0
+  //       -----------------
+  //               |
+  //               V
+  //        relocation area
+  case ELF::R_TILEGX_JUMPOFF_X1: {
+    uint64_t FinalAddress = Section.LoadAddress + Offset;
+    int64_t RealOffset = Value - FinalAddress;
+    int64_t TruncOffset = (RealOffset >> 3) & 0x7FFFFFFLL;
+    *TargetPtr = ((*TargetPtr) & (~(0x7FFFFFFLL << 31)))
+                  | (TruncOffset << 31);
+    break;
+  }
+
+  // R_TILEGX_IMM16_X0_HW2_LAST
+  //
+  // inst-bundle[27-12] = Value[47-32]
+  case ELF::R_TILEGX_IMM16_X0_HW2_LAST: {
+    uint64_t hw2 = (Value >> 32) & 0xFFFF;
+    *TargetPtr = ((*TargetPtr) & (~(0xFFFFLL << 12)))
+                  | (hw2 << 12);
+    break;
+  }
+
+  // R_TILEGX_IMM16_X1_HW2_LAST
+  //
+  // inst-bundle[58-43] = Value[47-32]
+  case ELF::R_TILEGX_IMM16_X1_HW2_LAST: {
+    uint64_t hw2 = (Value >> 32) & 0xFFFF;
+    *TargetPtr = ((*TargetPtr) & (~(0xFFFFLL << 43)))
+                  | (hw2 << 43);
+    break;
+  }
+
+  // R_TILEGX_IMM16_X0_HW1
+  //
+  // inst-bundle[27-12] = Value[31-16]
+  case ELF::R_TILEGX_IMM16_X0_HW1: {
+    uint64_t hw1 = (Value >> 16) & 0xFFFF;
+    *TargetPtr = ((*TargetPtr) & (~(0xFFFFLL << 12)))
+                  | (hw1 << 12);
+    break;
+  }
+
+  // R_TILEGX_IMM16_X1_HW1
+  //
+  // inst-bundle[58-43] = Value[31-16]
+  case ELF::R_TILEGX_IMM16_X1_HW1: {
+    uint64_t hw1 = (Value >> 16) & 0xFFFF;
+    *TargetPtr = ((*TargetPtr) & (~(0xFFFFLL << 43)))
+                  | (hw1 << 43);
+    break;
+  }
+
+  // R_TILEGX_IMM16_X0_HW0
+  //
+  // inst-bundle[27-12] = Value[15-0]
+  case ELF::R_TILEGX_IMM16_X0_HW0: {
+    uint64_t hw0 = Value & 0xFFFF;
+    *TargetPtr = ((*TargetPtr) & (~(0xFFFFLL << 12)))
+                  | (hw0 << 12);
+    break;
+  }
+
+  // R_TILEGX_IMM16_X1_HW0
+  //
+  // inst-bundle[58-43] = Value[15-0]
+  case ELF::R_TILEGX_IMM16_X1_HW0: {
+    uint64_t hw0 = Value & 0xFFFF;
+    *TargetPtr = ((*TargetPtr) & (~(0xFFFFLL << 43)))
+                  | (hw0 << 43);
+    break;
+  }
+  }
+}
+
 void RuntimeDyldELF::resolveRelocation(const SectionEntry &Section,
                                        uint64_t Offset,
                                        uint64_t Value,
@@ -588,6 +708,8 @@
     break;
   case Triple::ppc64:
     resolvePPC64Relocation(Section, Offset, Value, Type, Addend);
+  case Triple::tilegx:
+    resolveTileGXRelocation(Section, Offset, Value, Type, Addend);
     break;
   default: llvm_unreachable("Unsupported CPU type!");
   }
Index: lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
===================================================================
--- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
+++ lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
@@ -62,6 +62,12 @@
                               uint32_t Type,
                               int64_t Addend);
 
+  void resolveTileGXRelocation(const SectionEntry &Section,
+                               uint64_t Offset,
+                               uint64_t Value,
+                               uint32_t Type,
+                               int64_t Addend);
+
   virtual void resolveRelocation(const SectionEntry &Section,
                                  uint64_t Offset,
                                  uint64_t Value,
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