[PATCH] [RFC][3/17]TILE-Gx: add instruction template for tilegx

[Jiong WANG]

This patch implement the instruction definiation XXXInstrInfo.td file and XXXInstrInfo.cpp for TILE-Gx.

Generally, the implementation is straightforward, most of the work is done by referencing TILE-Gx ISA manual.

On thing tilegx backend different from other target is it's VLIW. and the instruction bundle for contains either 2 (X mode) or 3 (Y mode) instructions depending on the hardware resources.

For example, for the "add reg, reg, reg" instruction, it can be  issued in either X mode or Y mode.  This cause some trouble for MC Layer, because one instruction have several encoding candidates. The tilegx's way is to define one template for instruction matching, and several other for instruction encoding.

defm ADD: TileADD

multiclass TileADD {

  def #NAME#
     /* this is for instruction matching */

  def #0_X0#
  def #0_X1#
  def #0_Y0#
  def #0_Y1#
    /* these are for instruction encoding only */
    /* for the purpose that tablegen could exact necessary encoding info */
}

take one instruction bundle issued in Y mode for example:

Normal LLVM
          \
           \
            V
           scheduled instruction sequences
                \
                 \  TileGX bundling pass
                  \
                   V
                  bundled instruction sequences
                    |
                    |
                    V
      { opcode: ADD   | opcode: ADDI | opcode: LD }
                    |
                    |  Lower MachineInstr
                    |   to Machine Code Instr
                    V
      { opcode: ADD_Y0   | opcode: ADDI_Y1 | opcode: LD_Y2 }
                    |
                    |  final pass to encode
                   V
                  binary

Please review, thanks

---
Regards,
Jiong
Tilera Corporation.

http://llvm-reviews.chandlerc.com/D513
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