[PATCH] [RFC][1/17]TILE-Gx: recognize tilegx triple
Jiong WANG
wong.kwongyuan.llvm at gmail.com
Sun Mar 10 23:56:31 PDT 2013
Hi,
I split the TILE-Gx support into 17 parts, each one support one specific part of the back-end feature, in the aim of easying the code review.
this is the first patch which teach llvm to recognize tilegx triple.
please review, thanks
---
Regards,
Jiong
Tilera Corporation
http://llvm-reviews.chandlerc.com/D511
Files:
autoconf/configure.ac
configure
include/llvm/ADT/Triple.h
lib/Support/Triple.cpp
Index: autoconf/configure.ac
===================================================================
--- autoconf/configure.ac
+++ autoconf/configure.ac
@@ -402,6 +402,7 @@
hexagon-*) llvm_cv_target_arch="Hexagon" ;;
mblaze-*) llvm_cv_target_arch="MBlaze" ;;
nvptx-*) llvm_cv_target_arch="NVPTX" ;;
+ tilegx-*) llvm_cv_target_arch="Tile" ;;
*) llvm_cv_target_arch="Unknown" ;;
esac])
@@ -435,6 +436,7 @@
msp430-*) host_arch="MSP430" ;;
hexagon-*) host_arch="Hexagon" ;;
mblaze-*) host_arch="MBlaze" ;;
+ tilegx-*) host_arch="Tile" ;;
*) host_arch="Unknown" ;;
esac
@@ -780,13 +782,13 @@
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all or target1,target2,... Valid targets are:
host, x86, x86_64, sparc, powerpc, arm, aarch64, mips, hexagon,
- xcore, msp430, nvptx, and cpp (default=all)]),,
+ xcore, msp430, nvptx, tilegx, and cpp (default=all)]),,
enableval=all)
if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon Tile" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -805,6 +807,7 @@
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
+ tilegx) TARGETS_TO_BUILD="Tile $TARGETS_TO_BUILD" ;;
host) case "$llvm_cv_target_arch" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -817,6 +820,7 @@
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
NVPTX) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
+ Tile) TARGETS_TO_BUILD="Tile $TARGETS_TO_BUILD" ;;
*) AC_MSG_ERROR([Can not set target to build]) ;;
esac ;;
*) AC_MSG_ERROR([Unrecognized target $a_target]) ;;
Index: configure
===================================================================
--- configure
+++ configure
@@ -1440,7 +1440,7 @@
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
x86_64, sparc, powerpc, arm, aarch64, mips, hexagon,
- xcore, msp430, nvptx, and cpp (default=all)
+ xcore, msp430, nvptx, tilegx, and cpp (default=all)
--enable-experimental-targets
Build experimental host targets: disable or
target1,target2,... (default=disable)
@@ -4020,6 +4020,7 @@
hexagon-*) llvm_cv_target_arch="Hexagon" ;;
mblaze-*) llvm_cv_target_arch="MBlaze" ;;
nvptx-*) llvm_cv_target_arch="NVPTX" ;;
+ tilegx-*) llvm_cv_target_arch="Tile" ;;
*) llvm_cv_target_arch="Unknown" ;;
esac
fi
@@ -4053,6 +4054,7 @@
msp430-*) host_arch="MSP430" ;;
hexagon-*) host_arch="Hexagon" ;;
mblaze-*) host_arch="MBlaze" ;;
+ tilegx-*) host_arch="Tile" ;;
*) host_arch="Unknown" ;;
esac
@@ -5602,7 +5604,7 @@
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC AArch64 ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon Tile" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5621,6 +5623,7 @@
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
+ tilegx) TARGETS_TO_BUILD="Tile $TARGETS_TO_BUILD" ;;
host) case "$llvm_cv_target_arch" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5633,6 +5636,7 @@
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
NVPTX) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
+ Tile) TARGETS_TO_BUILD="Tile $TARGETS_TO_BUILD" ;;
*) { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
echo "$as_me: error: Can not set target to build" >&2;}
{ (exit 1); exit 1; }; } ;;
Index: include/llvm/ADT/Triple.h
===================================================================
--- include/llvm/ADT/Triple.h
+++ include/llvm/ADT/Triple.h
@@ -67,7 +67,8 @@
le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
amdil, // amdil: amd IL
spir, // SPIR: standard portable IR for OpenCL 32-bit version
- spir64 // SPIR: standard portable IR for OpenCL 64-bit version
+ spir64, // SPIR: standard portable IR for OpenCL 64-bit version
+ tilegx // Tile: tilegx
};
enum VendorType {
UnknownVendor,
Index: lib/Support/Triple.cpp
===================================================================
--- lib/Support/Triple.cpp
+++ lib/Support/Triple.cpp
@@ -44,6 +44,7 @@
case amdil: return "amdil";
case spir: return "spir";
case spir64: return "spir64";
+ case tilegx: return "tilegx";
}
llvm_unreachable("Invalid ArchType!");
@@ -87,6 +88,7 @@
case amdil: return "amdil";
case spir: return "spir";
case spir64: return "spir";
+ case tilegx: return "tile";
}
}
@@ -181,6 +183,7 @@
.Case("amdil", amdil)
.Case("spir", spir)
.Case("spir64", spir64)
+ .Case("tilegx", tilegx)
.Default(UnknownArch);
}
@@ -243,6 +246,7 @@
.Case("amdil", Triple::amdil)
.Case("spir", Triple::spir)
.Case("spir64", Triple::spir64)
+ .Case("tilegx", Triple::tilegx)
.Default(Triple::UnknownArch);
}
@@ -689,6 +693,7 @@
case llvm::Triple::sparcv9:
case llvm::Triple::x86_64:
case llvm::Triple::spir64:
+ case llvm::Triple::tilegx:
return 64;
}
llvm_unreachable("Invalid architecture value");
@@ -712,6 +717,7 @@
case Triple::UnknownArch:
case Triple::aarch64:
case Triple::msp430:
+ case Triple::tilegx:
T.setArch(UnknownArch);
break;
@@ -770,6 +776,7 @@
case Triple::ppc64:
case Triple::sparcv9:
case Triple::x86_64:
+ case Triple::tilegx:
// Already 64-bit.
break;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D511.1.patch
Type: text/x-patch
Size: 7162 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20130310/0175fdd9/attachment.bin>
More information about the llvm-commits
mailing list