[llvm] r175862 - Expand mips16 SelT form pseudso/macros.

[Cameron Zwarich]

I usually run locally with the verifier turned on for everything, and I noticed a few new errors like the one below. The cause appears to be that CmpRxRy16 is defined like this:

def CmpRxRy16: FRR16_ins<0b01010, "cmp", IIAlu> {
  let Defs = [T8];
}

The instruction class has a def of the first operand:

class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
  FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
        !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
}

You might want to consider adding -verify-machineinstrs as an argument to llc for tests like this. I suspect in the future we will turn the verifier (or some subset of it) on for all Asserts builds.

********************
FAIL: LLVM :: CodeGen/Mips/selTBteqzCmpi.ll (1508 of 7391)
******************** TEST 'LLVM :: CodeGen/Mips/selTBteqzCmpi.ll' FAILED ********************
Script:
--
/Users/zwarich/llvm-public/b/Release+Asserts/bin/llc -march=mipsel -mcpu=mips16 -relocation-model=pic < /Users/zwarich/llvm-public/l/test/CodeGen/Mips/selTBteqzCmpi.ll | /Users/zwarich/llvm-public/b/Release+Asserts/bin/FileCheck /Users/zwarich/llvm-public/l/test/CodeGen/Mips/selTBteqzCmpi.ll -check-prefix=16
--
Exit Code: 2
Command Output (stderr):
--

# After two-address instruction pass
# Machine code for function t: Post SSA

0B	BB#0: derived from LLVM BB %entry
16B		%vreg7<def> = LiRxImmX16 <es:_gp_disp>[TF=5]; CPU16Regs:%vreg7
32B		%vreg8<def> = AddiuRxPcImmX16 <es:_gp_disp>[TF=6]; CPU16Regs:%vreg8
48B		%vreg9<def> = SllX16 %vreg7, 16; CPU16Regs:%vreg9,%vreg7
64B		%vreg0<def> = AdduRxRyRz16 %vreg8, %vreg9; CPU16Regs:%vreg0,%vreg8,%vreg9
80B		%vreg1<def> = LwRxRyOffMemX16 %vreg0, <ga:@a>[TF=1], 0; mem:LD4[GOT] CPU16Regs:%vreg1,%vreg0
96B		%vreg2<def> = LwRxRyOffMemX16 %vreg1, 0, 0; mem:LD4[@a] CPU16Regs:%vreg2,%vreg1
112B		%vreg4<def> = LwRxRyOffMemX16 %vreg0, <ga:@i>[TF=1], 0; mem:LD4[GOT] CPU16Regs:%vreg4,%vreg0
128B		CmpiRxImmX16 %vreg2, 10, %T8<imp-def>; CPU16Regs:%vreg2
136B		%vreg10<def> = COPY %vreg4; CPU16Regs:%vreg10,%vreg4
144B		BteqzX16 <BB#2>, %T8<imp-use,kill>
	    Successors according to CFG: BB#1 BB#2

160B	BB#1: derived from LLVM BB %entry
	    Predecessors according to CFG: BB#0
176B		%vreg3<def> = LwRxRyOffMemX16 %vreg0, <ga:@j>[TF=1], 0; mem:LD4[GOT] CPU16Regs:%vreg3,%vreg0
184B		%vreg10<def> = COPY %vreg3<kill>; CPU16Regs:%vreg10,%vreg3
	    Successors according to CFG: BB#2

192B	BB#2: derived from LLVM BB %entry
	    Predecessors according to CFG: BB#0 BB#1
200B		%vreg5<def> = COPY %vreg10<kill>; CPU16Regs:%vreg5,%vreg10
224B		%vreg6<def> = LwRxRyOffMemX16 %vreg5, 0, 0; mem:LD4[<unknown>] CPU16Regs:%vreg6,%vreg5
240B		SwRxRyOffMemX16 %vreg6, %vreg4, 0, 0; mem:ST4[@i] CPU16Regs:%vreg6,%vreg4
256B		RetRA16

# End machine code for function t.

*** Bad machine code: Explicit definition marked as use ***
- function:    t
- basic block: BB#0 entry (0x7fd62882b9a0) [0B;160B)
- instruction: 128B	CmpiRxImmX16 %vreg2, 10, %T8<imp-def>; CPU16Regs:%vreg2
- operand 0:   %vreg2
LLVM ERROR: Found 1 machine code errors.
FileCheck error: '-' is empty.
--