Please review: X86 sext pattern optimization

[Nadav Rotem]

+  SDValue N1 = N->getOperand(1);
+  EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
+  DebugLoc dl = N->getDebugLoc();
+
+  
+  // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the

Extra space. 

+    if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256()) {
+      if (!ISD::isNormalLoad(N00.getNode()))
+        return SDValue();
+    }

No need for braces. 

LGTM. 

Thanks,
Nadav

On Feb 19, 2013, at 11:35 PM, "Demikhovsky, Elena" <elena.demikhovsky at intel.com> wrote:

> Too late. "Anyext" is translated before the lowering stage. I need the sequence (sext_in_reg (v4i64 anyext (v4i32 x )) as is.

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