[llvm] r175474 - Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
Reed Kotler
rkotler at mips.com
Mon Feb 18 16:20:58 PST 2013
Author: rkotler
Date: Mon Feb 18 18:20:58 2013
New Revision: 175474
URL: http://llvm.org/viewvc/llvm-project?rev=175474&view=rev
Log:
Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
Added:
llvm/trunk/test/CodeGen/Mips/seleqk.ll
llvm/trunk/test/CodeGen/Mips/selnek.ll
Modified:
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp?rev=175474&r1=175473&r2=175474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp Mon Feb 18 18:20:58 2013
@@ -139,6 +139,10 @@ bool Mips16InstrInfo::expandPostRAPseudo
case Mips::BteqzT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
break;
+ case Mips::BteqzT8CmpiX16:
+ ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
+ Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
+ break;
case Mips::BteqzT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
break;
@@ -150,6 +154,10 @@ bool Mips16InstrInfo::expandPostRAPseudo
case Mips::BtnezT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
break;
+ case Mips::BtnezT8CmpiX16:
+ ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
+ Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
+ break;
case Mips::BtnezT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
break;
@@ -433,6 +441,24 @@ void Mips16InstrInfo::ExpandFEXT_T8I816_
BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
}
+
+void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const {
+ unsigned regX = I->getOperand(0).getReg();
+ int64_t imm = I->getOperand(1).getImm();
+ MachineBasicBlock *target = I->getOperand(2).getMBB();
+ unsigned CmpOpc;
+ if (isUInt<8>(imm))
+ CmpOpc = CmpiOpc;
+ else if (isUInt<16>(imm))
+ CmpOpc = CmpiXOpc;
+ else
+ llvm_unreachable("immediate field not usable");
+ BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addImm(imm);
+ BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
+}
+
const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
if (validSpImm8(Imm))
return get(Mips::AddiuSpImm16);
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h?rev=175474&r1=175473&r2=175474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h Mon Feb 18 18:20:58 2013
@@ -118,6 +118,11 @@ private:
void ExpandFEXT_T8I816_ins(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned BtOpc, unsigned CmpOpc) const;
+
+ void ExpandFEXT_T8I8I16_ins(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+ unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const;
+
};
}
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=175474&r1=175473&r2=175474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Mon Feb 18 18:20:58 2013
@@ -51,6 +51,15 @@ class FI816_SP_ins<bits<3> _func, string
//
+class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
+ InstrItinClass itin>:
+ FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
+ !strconcat(asmstr, asmstr2), [], itin>;
+
+class FRI16_ins<bits<5> op, string asmstr,
+ InstrItinClass itin>:
+ FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
+
class F2RI16_ins<bits<5> _op, string asmstr,
InstrItinClass itin>:
FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
@@ -565,6 +574,24 @@ def CmpRxRy16: FRR16_ins<0b01010, "cmp",
let Defs = [T8];
}
+//
+// Format: CMPI rx, immediate MIPS16e
+// Purpose: Compare Immediate
+// To compare a constant with the contents of a GPR.
+//
+def CmpiRxImm16: FRI16_ins<0b01110, "cmpi", IIAlu> {
+ let Defs = [T8];
+}
+
+//
+// Format: CMPI rx, immediate MIPS16e
+// Purpose: Compare Immediate (Extended)
+// To compare a constant with the contents of a GPR.
+//
+def CmpiRxImmX16: FEXT_RI16_ins<0b01110, "cmpi", IIAlu> {
+ let Defs = [T8];
+}
+
//
// Format: DIV rx, ry MIPS16e
Added: llvm/trunk/test/CodeGen/Mips/seleqk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/seleqk.ll?rev=175474&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/seleqk.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/seleqk.ll Mon Feb 18 18:20:58 2013
@@ -0,0 +1,91 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+
+ at t = global i32 10, align 4
+ at f = global i32 199, align 4
+ at a = global i32 1, align 4
+ at b = global i32 1000, align 4
+ at z1 = common global i32 0, align 4
+ at z2 = common global i32 0, align 4
+ at z3 = common global i32 0, align 4
+ at z4 = common global i32 0, align 4
+ at .str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
+
+define void @calc_seleqk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp eq i32 %0, 1
+ br i1 %cmp, label %cond.true, label %cond.false
+
+cond.true: ; preds = %entry
+ %1 = load i32* @t, align 4
+ br label %cond.end
+
+cond.false: ; preds = %entry
+ %2 = load i32* @f, align 4
+ br label %cond.end
+
+cond.end: ; preds = %cond.false, %cond.true
+ %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
+ store i32 %cond, i32* @z1, align 4
+ %3 = load i32* @a, align 4
+ %cmp1 = icmp eq i32 %3, 1000
+ br i1 %cmp1, label %cond.true2, label %cond.false3
+
+cond.true2: ; preds = %cond.end
+ %4 = load i32* @f, align 4
+ br label %cond.end4
+
+cond.false3: ; preds = %cond.end
+ %5 = load i32* @t, align 4
+ br label %cond.end4
+
+cond.end4: ; preds = %cond.false3, %cond.true2
+ %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
+ store i32 %cond5, i32* @z2, align 4
+ %6 = load i32* @b, align 4
+ %cmp6 = icmp eq i32 %6, 3
+ br i1 %cmp6, label %cond.true7, label %cond.false8
+
+cond.true7: ; preds = %cond.end4
+ %7 = load i32* @f, align 4
+ br label %cond.end9
+
+cond.false8: ; preds = %cond.end4
+ %8 = load i32* @t, align 4
+ br label %cond.end9
+
+cond.end9: ; preds = %cond.false8, %cond.true7
+ %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
+ store i32 %cond10, i32* @z3, align 4
+ %9 = load i32* @b, align 4
+ %cmp11 = icmp eq i32 %9, 1000
+ br i1 %cmp11, label %cond.true12, label %cond.false13
+
+cond.true12: ; preds = %cond.end9
+ %10 = load i32* @t, align 4
+ br label %cond.end14
+
+cond.false13: ; preds = %cond.end9
+ %11 = load i32* @f, align 4
+ br label %cond.end14
+
+cond.end14: ; preds = %cond.false13, %cond.true12
+ %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ]
+ store i32 %cond15, i32* @z4, align 4
+ ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" }
+attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
+
+; 16: cmpi ${{[0-9]+}}, 1 # 16 bit inst
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
+
+; 16: cmpi ${{[0-9]+}}, 1000
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
+
+; 16: cmpi ${{[0-9]+}}, 3 # 16 bit inst
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
+
+; 16: cmpi ${{[0-9]+}}, 1000
+; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
Added: llvm/trunk/test/CodeGen/Mips/selnek.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/selnek.ll?rev=175474&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/selnek.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/selnek.ll Mon Feb 18 18:20:58 2013
@@ -0,0 +1,107 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+
+ at t = global i32 10, align 4
+ at f = global i32 199, align 4
+ at a = global i32 1, align 4
+ at b = global i32 1000, align 4
+ at z1 = common global i32 0, align 4
+ at z2 = common global i32 0, align 4
+ at z3 = common global i32 0, align 4
+ at z4 = common global i32 0, align 4
+ at .str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
+
+define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
+entry:
+ %0 = load i32* @a, align 4
+ %cmp = icmp ne i32 %0, 1
+ br i1 %cmp, label %cond.true, label %cond.false
+
+cond.true: ; preds = %entry
+ %1 = load i32* @f, align 4
+ br label %cond.end
+
+cond.false: ; preds = %entry
+ %2 = load i32* @t, align 4
+ br label %cond.end
+
+cond.end: ; preds = %cond.false, %cond.true
+ %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
+ store i32 %cond, i32* @z1, align 4
+ %3 = load i32* @a, align 4
+ %cmp1 = icmp ne i32 %3, 1000
+ br i1 %cmp1, label %cond.true2, label %cond.false3
+
+cond.true2: ; preds = %cond.end
+ %4 = load i32* @t, align 4
+ br label %cond.end4
+
+cond.false3: ; preds = %cond.end
+ %5 = load i32* @f, align 4
+ br label %cond.end4
+
+cond.end4: ; preds = %cond.false3, %cond.true2
+ %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
+ store i32 %cond5, i32* @z2, align 4
+ %6 = load i32* @b, align 4
+ %cmp6 = icmp ne i32 %6, 3
+ br i1 %cmp6, label %cond.true7, label %cond.false8
+
+cond.true7: ; preds = %cond.end4
+ %7 = load i32* @t, align 4
+ br label %cond.end9
+
+cond.false8: ; preds = %cond.end4
+ %8 = load i32* @f, align 4
+ br label %cond.end9
+
+cond.end9: ; preds = %cond.false8, %cond.true7
+ %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
+ store i32 %cond10, i32* @z3, align 4
+ %9 = load i32* @b, align 4
+ %cmp11 = icmp ne i32 %9, 1000
+ br i1 %cmp11, label %cond.true12, label %cond.false13
+
+cond.true12: ; preds = %cond.end9
+ %10 = load i32* @f, align 4
+ br label %cond.end14
+
+cond.false13: ; preds = %cond.end9
+ %11 = load i32* @t, align 4
+ br label %cond.end14
+
+cond.end14: ; preds = %cond.false13, %cond.true12
+ %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ]
+ store i32 %cond15, i32* @z4, align 4
+ ret void
+}
+
+define i32 @main() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
+entry:
+ call void @calc_z() "target-cpu"="mips16" "target-features"="+mips16,+o32"
+ %0 = load i32* @z1, align 4
+ %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %0) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+ %1 = load i32* @z2, align 4
+ %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %1) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+ %2 = load i32* @z3, align 4
+ %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %2) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+ %3 = load i32* @z4, align 4
+ %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %3) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+ ret i32 0
+}
+
+declare i32 @printf(i8*, ...) "target-cpu"="mips16" "target-features"="+mips16,+o32"
+
+attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" }
+attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
+
+; 16: cmpi ${{[0-9]+}}, 1 # 16 bit inst
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
+
+; 16: cmpi ${{[0-9]+}}, 1000
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
+
+; 16: cmpi ${{[0-9]+}}, 3 # 16 bit inst
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
+
+; 16: cmpi ${{[0-9]+}}, 1000
+; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
\ No newline at end of file
More information about the llvm-commits
mailing list