Please review: X86 sext pattern optimization

[Demikhovsky, Elena]

> Why is this a DAGCombine optimization and not a Lowering one ?   
Too late. "Anyext" is translated before the lowering stage. I need the sequence (sext_in_reg (v4i64 anyext (v4i32 x )) as is.

Added cost.

- Elena

-----Original Message-----
From: Nadav Rotem [mailto:nrotem at apple.com] 
Sent: Monday, February 18, 2013 02:03
To: Demikhovsky, Elena
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: Please review: X86 sext pattern optimization

Hi Elena, 

Thank you for working on this.  Why is this a DAGCombine optimization and not a Lowering one ?   Also, you need to update the cost model of the SEXT operations. Please add tests to the cost model to make sure that we estimate the costs of these casts correctly. 

Thanks,
Nadav


On Feb 17, 2013, at 1:20 AM, "Demikhovsky, Elena" <elena.demikhovsky at intel.com> wrote:

> 
> I optimized the following patterns:
> sext <4 x i1> to <4 x i64>
> sext <4 x i8> to <4 x i64>
> sext <4 x i16> to <4 x i64>
> 
> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
> (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 
> sext_in_reg (v4i32 x , ExtraVT)))
> 
> The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
> 
> The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.
> 
> 
> - Elena
> 
> 
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