[llvm] r174068 - Clarify intent.

[Jakob Stoklund Olesen]

Author: stoklund
Date: Thu Jan 31 11:56:23 2013
New Revision: 174068

URL: http://llvm.org/viewvc/llvm-project?rev=174068&view=rev
Log:
Clarify intent.

Modified:
    llvm/trunk/utils/TableGen/CodeGenRegisters.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=174068&r1=174067&r2=174068&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Thu Jan 31 11:56:23 2013
@@ -1198,6 +1198,12 @@ void CodeGenRegBank::computeSubRegIndexL
     if (Idx->getComposites().empty()) {
       Idx->LaneMask = 1u << Bit;
       // Share bit 31 in the unlikely case there are more than 32 leafs.
+      //
+      // Sharing bits is harmless; it allows graceful degradation in targets
+      // with more than 32 vector lanes. They simply get a limited resolution
+      // view of lanes beyond the 32nd.
+      //
+      // See also the comment for getSubRegIndexLaneMask().
       if (Bit < 31) ++Bit;
     } else {
       Idx->LaneMask = 0;