[llvm-commits] [llvm] r173620 - Legalizer: Add an assert and tweak a comment to clarify the assumptions this code makes.

[Benjamin Kramer]

Author: d0k
Date: Sun Jan 27 09:04:43 2013
New Revision: 173620

URL: http://llvm.org/viewvc/llvm-project?rev=173620&view=rev
Log:
Legalizer: Add an assert and tweak a comment to clarify the assumptions this code makes.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=173620&r1=173619&r2=173620&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sun Jan 27 09:04:43 2013
@@ -2098,9 +2098,13 @@ void DAGTypeLegalizer::ExpandIntRes_Shif
     EVT VT = LHSL.getValueType();
 
     // If the shift amount operand is coming from a vector legalization it may
-    // not have the right return type.  Fix that first by casting the operand.
+    // have an illegal type.  Fix that first by casting the operand.  Otherwise
+    // the new SHL_PARTS operation would need further legalization, and the
+    // legalizer assumes that illegal SHL_PARTS never occur.
     SDValue ShiftOp = N->getOperand(1);
     MVT ShiftTy = TLI.getShiftAmountTy(VT);
+    assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(VT.getSizeInBits()) &&
+           "ShiftAmountTy is too small to cover the range of this type!");
     if (ShiftOp.getValueType() != ShiftTy)
       ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);