[llvm-commits] [llvm] r172594 - in /llvm/trunk: lib/Target/Mips/AsmParser/MipsAsmParser.cpp lib/Target/Mips/Disassembler/MipsDisassembler.cpp lib/Target/Mips/MipsRegisterInfo.td test/MC/Disassembler/Mips/mips32.txt test/MC/Disassembler/Mips/mips32_le.txt test/MC/Mips/mips-alu-instructions.s test/MC/Mips/mips64-alu-instructions.s
Jack Carter
jcarter at mips.com
Tue Jan 15 17:29:10 PST 2013
Author: jacksprat
Date: Tue Jan 15 19:29:10 2013
New Revision: 172594
URL: http://llvm.org/viewvc/llvm-project?rev=172594&view=rev
Log:
reverting 172579
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
llvm/trunk/test/MC/Mips/mips-alu-instructions.s
llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=172594&r1=172593&r2=172594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Jan 15 19:29:10 2013
@@ -1071,9 +1071,6 @@
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
-
- if (!isMips64())
- return MatchOperand_NoMatch;
//if the first token is not '$' we have error
if (Parser.getTok().isNot(AsmToken::Dollar))
return MatchOperand_NoMatch;
@@ -1091,7 +1088,7 @@
MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
Parser.getTok().getLoc());
- op->setRegKind(MipsOperand::Kind_HW64Regs);
+ op->setRegKind(MipsOperand::Kind_HWRegs);
Operands.push_back(op);
Parser.Lex(); // Eat reg number
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=172594&r1=172593&r2=172594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Tue Jan 15 19:29:10 2013
@@ -128,11 +128,6 @@
uint64_t Address,
const void *Decoder);
-static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
- unsigned Insn,
- uint64_t Address,
- const void *Decoder);
-
static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@@ -459,17 +454,6 @@
return MCDisassembler::Success;
}
-static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
- unsigned RegNo,
- uint64_t Address,
- const void *Decoder) {
- //Currently only hardware register 29 is supported
- if (RegNo != 29)
- return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
- return MCDisassembler::Success;
-}
-
static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=172594&r1=172593&r2=172594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Tue Jan 15 19:29:10 2013
@@ -373,6 +373,6 @@
let ParserMatchClass = HWRegsAsmOperand;
}
-def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
+def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
let ParserMatchClass = HW64RegsAsmOperand;
}
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=172594&r1=172593&r2=172594&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32.txt Tue Jan 15 19:29:10 2013
@@ -404,9 +404,3 @@
# CHECK: xori $9, $6, 17767
0x38 0xc9 0x45 0x67
-
-# CHECK: .set push
-# CHECK: .set mips32r2
-# CHECK: rdhwr $5, $29
-# CHECK: .set pop
-0x7c 0x05 0xe8 0x3b
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=172594&r1=172593&r2=172594&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt Tue Jan 15 19:29:10 2013
@@ -404,9 +404,3 @@
# CHECK: xori $9, $6, 17767
0x67 0x45 0xc9 0x38
-
-# CHECK: .set push
-# CHECK: .set mips32r2
-# CHECK: rdhwr $5, $29
-# CHECK: .set pop
-0x3b 0xe8 0x05 0x7c
Modified: llvm/trunk/test/MC/Mips/mips-alu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-alu-instructions.s?rev=172594&r1=172593&r2=172594&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-alu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-alu-instructions.s Tue Jan 15 19:29:10 2013
@@ -81,10 +81,6 @@
# CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00]
# CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00]
# CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01]
-# CHECK: .set push
-# CHECK: .set mips32r2
-# CHECK: rdhwr $5, $29
-# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
add $9,$6,$7
add $9,$6,17767
addu $9,$6,-15001
@@ -102,4 +98,3 @@
neg $6,$7
negu $6,$7
move $7,$8
- rdhwr $5, $29
Modified: llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64-alu-instructions.s?rev=172594&r1=172593&r2=172594&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64-alu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips64-alu-instructions.s Tue Jan 15 19:29:10 2013
@@ -78,11 +78,6 @@
# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
# CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01]
-# CHECK: .set push
-# CHECK: .set mips32r2
-# CHECK: rdhwr $5, $29
-# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
-
dadd $9,$6,$7
dadd $9,$6,17767
daddu $9,$6,-15001
@@ -97,4 +92,3 @@
multu $3,$5
dsubu $4,$3,$5
move $7,$8
- rdhwr $5, $29
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