[llvm-commits] [llvm] r172322 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp test/CodeGen/PowerPC/vec_extload.ll

[Benjamin Kramer]

Author: d0k
Date: Sat Jan 12 13:06:44 2013
New Revision: 172322

URL: http://llvm.org/viewvc/llvm-project?rev=172322&view=rev
Log:
When lowering an inreg sext first shift left, then right arithmetically.

Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=172322&r1=172321&r2=172322&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Sat Jan 12 13:06:44 2013
@@ -508,9 +508,9 @@
 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
   EVT VT = Op.getValueType();
 
-  // Make sure that the SRA and SRL instructions are available.
+  // Make sure that the SRA and SHL instructions are available.
   if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
-      TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
+      TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
     return DAG.UnrollVectorOp(Op.getNode());
 
   DebugLoc DL = Op.getDebugLoc();
@@ -521,7 +521,7 @@
   SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
 
   Op = Op.getOperand(0);
-  Op =   DAG.getNode(ISD::SRL, DL, VT, Op, ShiftSz);
+  Op =   DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
   return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
 }
 

Modified: llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll?rev=172322&r1=172321&r2=172322&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_extload.ll Sat Jan 12 13:06:44 2013
@@ -15,7 +15,7 @@
   ret <16 x i8> %c
 }
 ; CHECK: v16si8_sext_in_reg:
-; CHECK: vsrb
+; CHECK: vslb
 ; CHECK: vsrab
 ; CHECK: blr 
 
@@ -37,7 +37,7 @@
   ret <8 x i16> %c
 }
 ; CHECK: v8si16_sext_in_reg:
-; CHECK: vsrh
+; CHECK: vslh
 ; CHECK: vsrah
 ; CHECK: blr 
 
@@ -61,7 +61,7 @@
   ret <4 x i32> %c
 }
 ; CHECK: v4si32_sext_in_reg:
-; CHECK: vsrw
+; CHECK: vslw
 ; CHECK: vsraw
 ; CHECK: blr