[llvm-commits] [llvm] r171073 - in /llvm/trunk: include/llvm/IntrinsicsPowerPC.td test/CodeGen/PowerPC/dcbt-sched.ll

Hal Finkel hfinkel at anl.gov
Tue Dec 25 10:51:19 PST 2012


Author: hfinkel
Date: Tue Dec 25 12:51:18 2012
New Revision: 171073

URL: http://llvm.org/viewvc/llvm-project?rev=171073&view=rev
Log:
Loosen scheduling restrictions on the PPC dcbt intrinsic

As with the prefetch intrinsic to which it maps, simply have dcbt
marked as reading from and writing to its arguments instead of having
unmodeled side effects. While this might cause unwanted code motion
(because aliasing checks don't really capture cache-line sharing),
it is more important that prefetches in unrolled loops don't block
the scheduler from rearranging the unrolled loop body.

Added:
    llvm/trunk/test/CodeGen/PowerPC/dcbt-sched.ll
Modified:
    llvm/trunk/include/llvm/IntrinsicsPowerPC.td

Modified: llvm/trunk/include/llvm/IntrinsicsPowerPC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsPowerPC.td?rev=171073&r1=171072&r2=171073&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsPowerPC.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsPowerPC.td Tue Dec 25 12:51:18 2012
@@ -22,7 +22,8 @@
   def int_ppc_dcbf  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
-  def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty],
+    [IntrReadWriteArgMem, NoCapture<0>]>;
   def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;

Added: llvm/trunk/test/CodeGen/PowerPC/dcbt-sched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/dcbt-sched.ll?rev=171073&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/dcbt-sched.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/dcbt-sched.ll Tue Dec 25 12:51:18 2012
@@ -0,0 +1,22 @@
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -mcpu=a2 -enable-misched -enable-aa-sched-mi < %s | FileCheck %s
+
+define i8 @test1(i8* noalias %a, i8* noalias %b, i8* noalias %c) nounwind {
+entry:
+  %q = load i8* %b
+  call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
+  %r = load i8* %c
+  %s = add i8 %q, %r
+  ret i8 %s
+}
+
+declare void @llvm.prefetch(i8*, i32, i32, i32)
+
+; Test that we've moved the second load to before the dcbt to better
+; hide its latency.
+; CHECK: @test1
+; CHECK: lbz
+; CHECK: lbz
+; CHECK: dcbt
+





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