[llvm-commits] [llvm] r170620 - in /llvm/trunk/lib/Target/R600: AMDILCFGStructurizer.cpp R600InstrInfo.cpp SIInstrInfo.cpp

[Jakob Stoklund Olesen]

On Dec 19, 2012, at 4:29 PM, NAKAMURA Takumi <geek4civic at gmail.com> wrote:

> Jakob and Tom, please confirm my change, thank you.

Thanks for fixing it, Takumi. It looks fine to me.

As Owen said, this code should really be using BuildMI().

/jakob

> 
> ...Takumi
> 
> 2012/12/20 NAKAMURA Takumi <geek4civic at gmail.com>:
>> Author: chapuni
>> Date: Wed Dec 19 18:22:11 2012
>> New Revision: 170620
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=170620&view=rev
>> Log:
>> Target/R600: Update MIB according to r170588.
>> 
>> Modified:
>>    llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp
>>    llvm/trunk/lib/Target/R600/R600InstrInfo.cpp
>>    llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
>> 
>> Modified: llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp?rev=170620&r1=170619&r2=170620&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp (original)
>> +++ llvm/trunk/lib/Target/R600/AMDILCFGStructurizer.cpp Wed Dec 19 18:22:11 2012
>> @@ -2022,7 +2022,9 @@
>>       CFGTraits::insertAssignInstrBefore(insertPos, passRep, immReg, 1);
>>       InstrT *newInstr =
>>         CFGTraits::insertInstrBefore(insertPos, AMDGPU::BRANCH_COND_i32, passRep);
>> -      MachineInstrBuilder(newInstr).addMBB(loopHeader).addReg(immReg, false);
>> +      MachineInstrBuilder MIB(*funcRep, newInstr);
>> +      MIB.addMBB(loopHeader);
>> +      MIB.addReg(immReg, false);
>> 
>>       SHOWNEWINSTR(newInstr);
>> 
>> @@ -2844,13 +2846,12 @@
>>     MachineInstr *oldInstr = &(*instrPos);
>>     const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
>>     MachineBasicBlock *blk = oldInstr->getParent();
>> -    MachineInstr *newInstr =
>> -      blk->getParent()->CreateMachineInstr(tii->get(newOpcode),
>> -                                           DL);
>> +    MachineFunction *MF = blk->getParent();
>> +    MachineInstr *newInstr = MF->CreateMachineInstr(tii->get(newOpcode), DL);
>> 
>>     blk->insert(instrPos, newInstr);
>> -    MachineInstrBuilder(newInstr).addReg(oldInstr->getOperand(1).getReg(),
>> -                                         false);
>> +    MachineInstrBuilder MIB(*MF, newInstr);
>> +    MIB.addReg(oldInstr->getOperand(1).getReg(), false);
>> 
>>     SHOWNEWINSTR(newInstr);
>>     //erase later oldInstr->eraseFromParent();
>> @@ -2863,13 +2864,13 @@
>>                                      RegiT regNum,
>>                                      DebugLoc DL) {
>>     const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
>> +    MachineFunction *MF = blk->getParent();
>> 
>> -    MachineInstr *newInstr =
>> -      blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DL);
>> +    MachineInstr *newInstr = MF->CreateMachineInstr(tii->get(newOpcode), DL);
>> 
>>     //insert before
>>     blk->insert(insertPos, newInstr);
>> -    MachineInstrBuilder(newInstr).addReg(regNum, false);
>> +    MachineInstrBuilder(*MF, newInstr).addReg(regNum, false);
>> 
>>     SHOWNEWINSTR(newInstr);
>>   } //insertCondBranchBefore
>> @@ -2879,11 +2880,12 @@
>>                                   AMDGPUCFGStructurizer *passRep,
>>                                   RegiT regNum) {
>>     const TargetInstrInfo *tii = passRep->getTargetInstrInfo();
>> +    MachineFunction *MF = blk->getParent();
>>     MachineInstr *newInstr =
>> -      blk->getParent()->CreateMachineInstr(tii->get(newOpcode), DebugLoc());
>> +      MF->CreateMachineInstr(tii->get(newOpcode), DebugLoc());
>> 
>>     blk->push_back(newInstr);
>> -    MachineInstrBuilder(newInstr).addReg(regNum, false);
>> +    MachineInstrBuilder(*MF, newInstr).addReg(regNum, false);
>> 
>>     SHOWNEWINSTR(newInstr);
>>   } //insertCondBranchEnd
>> @@ -2928,12 +2930,14 @@
>>                                        RegiT src2Reg) {
>>     const AMDGPUInstrInfo *tii =
>>              static_cast<const AMDGPUInstrInfo *>(passRep->getTargetInstrInfo());
>> +    MachineFunction *MF = blk->getParent();
>>     MachineInstr *newInstr =
>> -      blk->getParent()->CreateMachineInstr(tii->get(tii->getIEQOpcode()), DebugLoc());
>> +      MF->CreateMachineInstr(tii->get(tii->getIEQOpcode()), DebugLoc());
>> 
>> -    MachineInstrBuilder(newInstr).addReg(dstReg, RegState::Define); //set target
>> -    MachineInstrBuilder(newInstr).addReg(src1Reg); //set src value
>> -    MachineInstrBuilder(newInstr).addReg(src2Reg); //set src value
>> +    MachineInstrBuilder MIB(*MF, newInstr);
>> +    MIB.addReg(dstReg, RegState::Define); //set target
>> +    MIB.addReg(src1Reg); //set src value
>> +    MIB.addReg(src2Reg); //set src value
>> 
>>     blk->insert(instrPos, newInstr);
>>     SHOWNEWINSTR(newInstr);
>> 
>> Modified: llvm/trunk/lib/Target/R600/R600InstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600InstrInfo.cpp?rev=170620&r1=170619&r2=170620&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/R600/R600InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/R600/R600InstrInfo.cpp Wed Dec 19 18:22:11 2012
>> @@ -72,10 +72,11 @@
>> MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
>>                                              unsigned DstReg, int64_t Imm) const {
>>   MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
>> -  MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
>> -  MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
>> -  MachineInstrBuilder(MI).addImm(Imm);
>> -  MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT
>> +  MachineInstrBuilder MIB(*MF, MI);
>> +  MIB.addReg(DstReg, RegState::Define);
>> +  MIB.addReg(AMDGPU::ALU_LITERAL_X);
>> +  MIB.addImm(Imm);
>> +  MIB.addReg(0); // PREDICATE_BIT
>> 
>>   return MI;
>> }
>> @@ -449,7 +450,8 @@
>>   if (PIdx != -1) {
>>     MachineOperand &PMO = MI->getOperand(PIdx);
>>     PMO.setReg(Pred[2].getReg());
>> -    MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
>> +    MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
>> +    MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
>>     return true;
>>   }
>> 
>> 
>> Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=170620&r1=170619&r2=170620&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Wed Dec 19 18:22:11 2012
>> @@ -62,8 +62,9 @@
>> MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
>>                                            int64_t Imm) const {
>>   MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
>> -  MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
>> -  MachineInstrBuilder(MI).addImm(Imm);
>> +  MachineInstrBuilder MIB(*MF, MI);
>> +  MIB.addReg(DstReg, RegState::Define);
>> +  MIB.addImm(Imm);
>> 
>>   return MI;
>> 
>> 
>> 
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