[llvm-commits] [llvm] r170551 - in /llvm/trunk: lib/Target/PowerPC/PPCISelLowering.cpp test/CodeGen/PowerPC/vec_select.ll

Benjamin Kramer benny.kra at googlemail.com
Wed Dec 19 07:49:15 PST 2012


Author: d0k
Date: Wed Dec 19 09:49:14 2012
New Revision: 170551

URL: http://llvm.org/viewvc/llvm-project?rev=170551&view=rev
Log:
PowerPC: Expand VSELECT nodes.

There's probably a better expansion for those nodes than the default for
altivec, but this is better than crashing. VSELECTs occur in loop vectorizer
output.

Added:
    llvm/trunk/test/CodeGen/PowerPC/vec_select.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=170551&r1=170550&r2=170551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Dec 19 09:49:14 2012
@@ -376,6 +376,7 @@
       setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
       setOperationAction(ISD::CTTZ, VT, Expand);
       setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
+      setOperationAction(ISD::VSELECT, VT, Expand);
       setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
 
       for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;

Added: llvm/trunk/test/CodeGen/PowerPC/vec_select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_select.ll?rev=170551&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_select.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_select.ll Wed Dec 19 09:49:14 2012
@@ -0,0 +1,7 @@
+; RUN: llc < %s -mtriple=powerpc64-linux-gnu -mattr=+altivec | FileCheck %s
+
+; CHECK: vsel_float
+define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
+  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
+  ret <4 x float> %vsel
+}





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