[llvm-commits] [llvm] r170523 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[NAKAMURA Takumi]

Author: chapuni
Date: Wed Dec 19 04:12:48 2012
New Revision: 170523

URL: http://llvm.org/viewvc/llvm-project?rev=170523&view=rev
Log:
X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=170523&r1=170522&r2=170523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Dec 19 04:12:48 2012
@@ -15934,8 +15934,8 @@
   // TODO: It is possible to support ZExt by zeroing the undef values
   // during the shuffle phase or after the shuffle.
   if (RegVT.isVector() && RegVT.isInteger() &&
-      (Ext == ISD::EXTLOAD && Subtarget->hasSSSE3() ||
-       Ext == ISD::SEXTLOAD && Subtarget->hasSSE41())){
+      ((Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) ||
+       (Ext == ISD::SEXTLOAD && Subtarget->hasSSE41()))){
     assert(MemVT != RegVT && "Cannot extend to the same type");
     assert(MemVT.isVector() && "Must load a vector from memory");