[llvm-commits] [llvm] r170104 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Mips/

Chad Rosier mcrosier at apple.com
Mon Dec 17 12:04:39 PST 2012


Hi Patrik,
Thanks for cleaning this up.  I fixed a few more things in r170360.  I believe everything is in order now.  Thanks, Patrik.

 Chad


On Dec 17, 2012, at 6:38 AM, Patrik Hägglund H <patrik.h.hagglund at ericsson.com> wrote:

> Hi Chad,
> 
> I tried to address your concerns in r170336.
> 
> I have left most of the changes, as seen in the diff below, between r170103 (before my initial change), and r170336. I hope that all of them now are safe. Please tell me if you still have concerns.
> 
> /Patrik Hägglund
> 
> diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
> index e900c6b..b704253 100644
> --- a/lib/CodeGen/SelectionDAG/FastISel.cpp
> +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
> @@ -737,15 +737,15 @@ bool FastISel::SelectBitCast(const User *I) {
>   }
> 
>   // Bitcasts of other values become reg-reg copies or BITCAST operators.
> -  EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
> -  EVT DstVT = TLI.getValueType(I->getType());
> -
> -  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
> -      DstVT == MVT::Other || !DstVT.isSimple() ||
> -      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
> +  EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
> +  EVT DstEVT = TLI.getValueType(I->getType());
> +  if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
> +      !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
>     // Unhandled type. Halt "fast" selection and bail.
>     return false;
> 
> +  MVT SrcVT = SrcEVT.getSimpleVT();
> +  MVT DstVT = DstEVT.getSimpleVT();
>   unsigned Op0 = getRegForValue(I->getOperand(0));
>   if (Op0 == 0)
>     // Unhandled operand. Halt "fast" selection and bail.
> @@ -755,7 +755,7 @@ bool FastISel::SelectBitCast(const User *I) {
> 
>   // First, try to perform the bitcast by inserting a reg-reg copy.
>   unsigned ResultReg = 0;
> -  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
> +  if (SrcVT == DstVT) {
>     const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
>     const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
>     // Don't attempt a cross-class copy. It will likely fail.
> @@ -768,8 +768,7 @@ bool FastISel::SelectBitCast(const User *I) {
> 
>   // If the reg-reg copy failed, select a BITCAST opcode.
>   if (!ResultReg)
> -    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
> -                           ISD::BITCAST, Op0, Op0IsKill);
> +    ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
> 
>   if (!ResultReg)
>     return false;
> diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
> index c3a5e64..18690db 100644
> --- a/lib/Target/ARM/ARMFastISel.cpp
> +++ b/lib/Target/ARM/ARMFastISel.cpp
> @@ -178,24 +178,24 @@ class ARMFastISel : public FastISel {
>     bool isLoadTypeLegal(Type *Ty, MVT &VT);
>     bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
>                     bool isZExt);
> -    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
> +    bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
>                      unsigned Alignment = 0, bool isZExt = true,
>                      bool allocReg = true);
> -    bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
> +    bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
>                       unsigned Alignment = 0);
>     bool ARMComputeAddress(const Value *Obj, Address &Addr);
>     void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
>     bool ARMIsMemCpySmall(uint64_t Len);
>     bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
>                                unsigned Alignment);
> -    unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
> -    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
> -    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
> -    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
> -    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
> -    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
> +    unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
> +    unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
> +    unsigned ARMMaterializeInt(const Constant *C, MVT VT);
> +    unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
> +    unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
> +    unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
>     unsigned ARMSelectCallOp(bool UseReg);
> -    unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, EVT VT);
> +    unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
> 
>     // Call handling routines.
>   private:
> @@ -487,7 +487,7 @@ unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
> 
> // TODO: Don't worry about 64-bit now, but when this is fixed remove the
> // checks from the various callers.
> -unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
> +unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
>   if (VT == MVT::f64) return 0;
> 
>   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
> @@ -497,7 +497,7 @@ unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
>   return MoveReg;
> }
> 
> -unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
> +unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
>   if (VT == MVT::i64) return 0;
> 
>   unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
> @@ -510,7 +510,7 @@ unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
> // For double width floating point we need to materialize two constants
> // (the high and the low) into integer registers then use a move to get
> // the combined constant into an FP reg.
> -unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
> +unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
>   const APFloat Val = CFP->getValueAPF();
>   bool is64bit = VT == MVT::f64;
> 
> @@ -554,7 +554,7 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
>   return DestReg;
> }
> 
> -unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
> +unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
> 
>   if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
>     return false;
> @@ -616,7 +616,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
>   return DestReg;
> }
> 
> -unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
> +unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
>   // For now 32-bit only.
>   if (VT != MVT::i32) return 0;
> 
> @@ -719,10 +719,11 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
> }
> 
> unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
> -  EVT VT = TLI.getValueType(C->getType(), true);
> +  EVT CEVT = TLI.getValueType(C->getType(), true);
> 
>   // Only handle simple types.
> -  if (!VT.isSimple()) return 0;
> +  if (!CEVT.isSimple()) return 0;
> +  MVT VT = CEVT.getSimpleVT();
> 
>   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
>     return ARMMaterializeFP(CFP, VT);
> @@ -1003,14 +1004,13 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
>   AddOptionalDefs(MIB);
> }
> 
> -bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
> +bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
>                               unsigned Alignment, bool isZExt, bool allocReg) {
> -  assert(VT.isSimple() && "Non-simple types are invalid here!");
>   unsigned Opc;
>   bool useAM3 = false;
>   bool needVMOV = false;
>   const TargetRegisterClass *RC;
> -  switch (VT.getSimpleVT().SimpleTy) {
> +  switch (VT.SimpleTy) {
>     // This is mostly going to be Neon/vector support.
>     default: return false;
>     case MVT::i1:
> @@ -1127,11 +1127,11 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
>   return true;
> }
> 
> -bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
> +bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
>                                unsigned Alignment) {
>   unsigned StrOpc;
>   bool useAM3 = false;
> -  switch (VT.getSimpleVT().SimpleTy) {
> +  switch (VT.SimpleTy) {
>     // This is mostly going to be Neon/vector support.
>     default: return false;
>     case MVT::i1: {
> @@ -1405,8 +1405,9 @@ bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
> bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
>                              bool isZExt) {
>   Type *Ty = Src1Value->getType();
> -  EVT SrcVT = TLI.getValueType(Ty, true);
> -  if (!SrcVT.isSimple()) return false;
> +  EVT SrcEVT = TLI.getValueType(Ty, true);
> +  if (!SrcEVT.isSimple()) return false;
> +  MVT SrcVT = SrcEVT.getSimpleVT();
> 
>   bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
>   if (isFloat && !Subtarget->hasVFP2())
> @@ -1443,7 +1444,7 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
>   unsigned CmpOpc;
>   bool isICmp = true;
>   bool needsExt = false;
> -  switch (SrcVT.getSimpleVT().SimpleTy) {
> +  switch (SrcVT.SimpleTy) {
>     default: return false;
>     // TODO: Verify compares.
>     case MVT::f32:
> @@ -1595,7 +1596,10 @@ bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
>     return false;
> 
>   Value *Src = I->getOperand(0);
> -  EVT SrcVT = TLI.getValueType(Src->getType(), true);
> +  EVT SrcEVT = TLI.getValueType(Src->getType(), true);
> +  if (!SrcEVT.isSimple())
> +    return false;
> +  MVT SrcVT = SrcEVT.getSimpleVT();
>   if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
>     return false;
> 
> @@ -1604,7 +1608,7 @@ bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
> 
>   // Handle sign-extension.
>   if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
> -    EVT DestVT = MVT::i32;
> +    MVT DestVT = MVT::i32;
>     SrcReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT,
>                                        /*isZExt*/!isSigned);
>     if (SrcReg == 0) return false;
> @@ -1842,7 +1846,7 @@ bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
>   unsigned Op2 = getRegForValue(I->getOperand(1));
>   if (Op2 == 0) return false;
> 
> -  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
> +  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.getSimpleVT()));
>   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
>                           TII.get(Opc), ResultReg)
>                   .addReg(Op1).addReg(Op2));
> @@ -2055,7 +2059,7 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
>     if (RVLocs.size() == 2 && RetVT == MVT::f64) {
>       // For this move we copy into two registers and then move into the
>       // double fp reg we want.
> -      EVT DestVT = RVLocs[0].getValVT();
> +      MVT DestVT = RVLocs[0].getValVT();
>       const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
>       unsigned ResultReg = createResultReg(DstRC);
>       AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> @@ -2070,7 +2074,7 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
>       UpdateValueMap(I, ResultReg);
>     } else {
>       assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
> -      EVT CopyVT = RVLocs[0].getValVT();
> +      MVT CopyVT = RVLocs[0].getValVT();
> 
>       // Special handling for extended integers.
>       if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
> @@ -2129,8 +2133,8 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
>       return false;
> 
>     unsigned SrcReg = Reg + VA.getValNo();
> -    EVT RVVT = TLI.getValueType(RV->getType());
> -    EVT DestVT = VA.getValVT();
> +    MVT RVVT = TLI.getSimpleValueType(RV->getType());
> +    MVT DestVT = VA.getValVT();
>     // Special handling for extended integers.
>     if (RVVT != DestVT) {
>       if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
> @@ -2175,7 +2179,7 @@ unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
> unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
>   GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
>                                        GlobalValue::ExternalLinkage, 0, Name);
> -  return ARMMaterializeGV(GV, TLI.getValueType(GV->getType()));
> +  return ARMMaterializeGV(GV, TLI.getSimpleValueType(GV->getType()));
> }
> 
> // A quick function that will emit a call for a named libcall in F with the
> @@ -2587,7 +2591,7 @@ bool ARMFastISel::SelectTrunc(const Instruction *I) {
>   return true;
> }
> 
> -unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
> +unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, EVT DestVT,
>                                     bool isZExt) {
>   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
>     return 0;
> @@ -2595,8 +2599,7 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
>   unsigned Opc;
>   bool isBoolZext = false;
>   const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
> -  if (!SrcVT.isSimple()) return 0;
> -  switch (SrcVT.getSimpleVT().SimpleTy) {
> +  switch (SrcVT.SimpleTy) {
>   default: return 0;
>   case MVT::i16:
>     if (!Subtarget->hasV6Ops()) return 0;
> @@ -2643,14 +2646,13 @@ bool ARMFastISel::SelectIntExt(const Instruction *I) {
>   Value *Src = I->getOperand(0);
>   Type *SrcTy = Src->getType();
> 
> -  EVT SrcVT, DestVT;
> -  SrcVT = TLI.getValueType(SrcTy, true);
> -  DestVT = TLI.getValueType(DestTy, true);
> -
>   bool isZExt = isa<ZExtInst>(I);
>   unsigned SrcReg = getRegForValue(Src);
>   if (!SrcReg) return false;
> 
> +  MVT SrcVT = TLI.getSimpleValueType(SrcTy, true);
> +  EVT DestVT = TLI.getValueType(DestTy, true);
> +
>   unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
>   if (ResultReg == 0) return false;
>   UpdateValueMap(I, ResultReg);
> @@ -2830,7 +2832,7 @@ bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
> }
> 
> unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
> -                                     unsigned Align, EVT VT) {
> +                                     unsigned Align, MVT VT) {
>   bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
>   ARMConstantPoolConstant *CPV =
>     ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
> 
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Patrik Hägglund H
> Sent: den 14 december 2012 14:16
> To: Chad Rosier
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [llvm] r170104 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Mips/
> 
> Sorry! My understanding of FastISel is limited, and these changes was obviously too aggressive. I can also see more changes that are wrong. I will go through all changes for FastIsel again, and try to correct this.
> 
> /Patrik Hägglund
> 
> -----Original Message-----
> From: Chad Rosier [mailto:mcrosier at apple.com]
> Sent: den 13 december 2012 21:57
> To: Patrik Hägglund H
> Cc: llvm-commits at cs.uiuc.edu; Jim Grosbach
> Subject: Re: [llvm-commits] [llvm] r170104 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Mips/
> 
> Patrik,
> I have a few concerns here.  See comments inline below.
> 
> On Dec 12, 2012, at 10:34 PM, Patrik Hagglund <patrik.h.hagglund at ericsson.com> wrote:
> 
>> Author: patha
>> Date: Thu Dec 13 00:34:11 2012
>> New Revision: 170104
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=170104&view=rev
>> Log:
>> Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
>> 
>> Accordingly, add helper funtions getSimpleValueType (in parallel to
>> getValueType) in SDValue, SDNode, and TargetLowering.
>> 
>> This is the first, in a series of patches.
>> 
>> This is the second attempt. In the first attempt (r169837), a few
>> getSimpleVT() were hoisted too far, detected by bootstrap failures.
>> 
>> Modified:
>>   llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
>>   llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>>   llvm/trunk/include/llvm/Target/TargetLowering.h
>>   llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>>   llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
>>   llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>>   llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>>   llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>   llvm/trunk/lib/Target/ARM/ARMISelLowering.h
>>   llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> 
>> Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Fu
>> nctionLoweringInfo.h?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Thu Dec 13
>> +++ 00:34:11 2012
>> @@ -136,7 +136,7 @@
>>    return ValueMap.count(V);
>>  }
>> 
>> -  unsigned CreateReg(EVT VT);
>> +  unsigned CreateReg(MVT VT);
>> 
>>  unsigned CreateRegs(Type *Ty);
>> 
>> 
>> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Se
>> lectionDAGNodes.h?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
>> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Dec 13
>> +++ 00:34:11 2012
>> @@ -130,6 +130,11 @@
>>  ///
>>  inline EVT getValueType() const;
>> 
>> +  /// Return the simple ValueType of the referenced return value.
>> +  MVT getSimpleValueType() const {
>> +    return getValueType().getSimpleVT();  }
>> +
>>  /// getValueSizeInBits - Returns the size of the value in bits.
>>  ///
>>  unsigned getValueSizeInBits() const { @@ -595,6 +600,12 @@
>>    return ValueList[ResNo];
>>  }
>> 
>> +  /// Return the type of a specified result as a simple type.
>> +  ///
>> +  MVT getSimpleValueType(unsigned ResNo) const {
>> +    return getValueType(ResNo).getSimpleVT();
>> +  }
>> +
>>  /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
>>  ///
>>  unsigned getValueSizeInBits(unsigned ResNo) const {
>> 
>> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Tar
>> getLowering.h?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
>> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Dec 13
>> +++ 00:34:11 2012
>> @@ -232,9 +232,8 @@
>> 
>>  /// getRegClassFor - Return the register class that should be used for the
>>  /// specified value type.
>> -  virtual const TargetRegisterClass *getRegClassFor(EVT VT) const {
>> -    assert(VT.isSimple() && "getRegClassFor called on illegal type!");
>> -    const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
>> +  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
>> +    const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
>>    assert(RC && "This value type is not natively supported!");
>>    return RC;
>>  }
>> @@ -578,7 +577,11 @@
>>    }
>>    return EVT::getEVT(Ty, AllowUnknown);
>>  }
>> -
>> +
>> +  /// Return the MVT corresponding to this LLVM type. See getValueType.
>> +  MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
>> +    return getValueType(Ty, AllowUnknown).getSimpleVT();  }
>> 
>>  /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
>>  /// function arguments in the caller parameter area.  This is the 
>> actual
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA
>> G/FastISel.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Dec 13
>> +++ 00:34:11 2012
>> @@ -737,11 +737,10 @@
>>  }
>> 
>>  // Bitcasts of other values become reg-reg copies or BITCAST operators.
>> -  EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
>> -  EVT DstVT = TLI.getValueType(I->getType());
>> +  MVT SrcVT = TLI.getSimpleValueType(I->getOperand(0)->getType());
>> +  MVT DstVT = TLI.getSimpleValueType(I->getType());
>> 
>> -  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
>> -      DstVT == MVT::Other || !DstVT.isSimple() ||
>> +  if (SrcVT == MVT::Other || DstVT == MVT::Other ||
>>      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
>>    // Unhandled type. Halt "fast" selection and bail.
>>    return false;
>> @@ -755,7 +754,7 @@
>> 
>>  // First, try to perform the bitcast by inserting a reg-reg copy.
>>  unsigned ResultReg = 0;
>> -  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
>> +  if (SrcVT == DstVT) {
>>    const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
>>    const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
>>    // Don't attempt a cross-class copy. It will likely fail.
>> @@ -768,8 +767,7 @@
>> 
>>  // If the reg-reg copy failed, select a BITCAST opcode.
>>  if (!ResultReg)
>> -    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
>> -                           ISD::BITCAST, Op0, Op0IsKill);
>> +    ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, 
>> + Op0IsKill);
>> 
>>  if (!ResultReg)
>>    return false;
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA
>> G/FunctionLoweringInfo.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Thu 
>> +++ Dec 13 00:34:11 2012
>> @@ -208,7 +208,7 @@
>> }
>> 
>> /// CreateReg - Allocate a single virtual register for the given type.
>> -unsigned FunctionLoweringInfo::CreateReg(EVT VT) {
>> +unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
>>  return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
>> }
>> 
>> @@ -226,7 +226,7 @@
>>  unsigned FirstReg = 0;
>>  for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
>>    EVT ValueVT = ValueVTs[Value];
>> -    EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
>> +    MVT RegisterVT = TLI.getRegisterType(Ty->getContext(),
>> + ValueVT).getSimpleVT();
>> 
>>    unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
>>    for (unsigned i = 0; i != NumRegs; ++i) {
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA
>> G/InstrEmitter.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Dec 13
>> +++ 00:34:11 2012
>> @@ -99,7 +99,7 @@
>>  // the CopyToReg'd destination register instead of creating a new vreg.
>>  bool MatchReg = true;
>>  const TargetRegisterClass *UseRC = NULL;
>> -  EVT VT = Node->getValueType(ResNo);
>> +  MVT VT = Node->getSimpleValueType(ResNo);
>> 
>>  // Stick to the preferred register classes for legal types.
>>  if (TLI->isTypeLegal(VT))
>> @@ -124,7 +124,7 @@
>>          SDValue Op = User->getOperand(i);
>>          if (Op.getNode() != Node || Op.getResNo() != ResNo)
>>            continue;
>> -          EVT VT = Node->getValueType(Op.getResNo());
>> +          MVT VT = Node->getSimpleValueType(Op.getResNo());
>>          if (VT == MVT::Other || VT == MVT::Glue)
>>            continue;
>>          Match = false;
>> @@ -272,7 +272,8 @@
>>    // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
>>    // does not include operand register class info.
>>    if (!VReg) {
>> -      const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
>> +      const TargetRegisterClass *RC =
>> +        TLI->getRegClassFor(Op.getSimpleValueType());
>>      VReg = MRI->createVirtualRegister(RC);
>>    }
>>    BuildMI(*MBB, InsertPos, Op.getDebugLoc(), @@ -426,7 +427,7 @@ }
>> 
>> unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
>> -                                          EVT VT, DebugLoc DL) {
>> +                                          MVT VT, DebugLoc DL) {
>>  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
>>  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, 
>> SubIdx);
>> 
>> @@ -477,7 +478,8 @@
>>    // constraints on the %dst register, COPY can target all legal register
>>    // classes.
>>    unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
>> -    const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0));
>> +    const TargetRegisterClass *TRC =
>> +      TLI->getRegClassFor(Node->getSimpleValueType(0));
>> 
>>    unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
>>    MachineInstr *DefMI = MRI->getVRegDef(VReg); @@ -500,7 +502,7 @@
>>      // constrain its register class or issue a COPY to a compatible register
>>      // class.
>>      VReg = ConstrainForSubReg(VReg, SubIdx,
>> -                                Node->getOperand(0).getValueType(),
>> +                                
>> + Node->getOperand(0).getSimpleValueType(),
>>                                Node->getDebugLoc());
>> 
>>      // Create the destreg if it is missing.
>> @@ -532,7 +534,7 @@
>>    //
>>    // There is no constraint on the %src register class.
>>    //
>> -    const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
>> +    const TargetRegisterClass *SRC =
>> + TLI->getRegClassFor(Node->getSimpleValueType(0));
>>    SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
>>    assert(SRC && "No register class supports VT and SubIdx for 
>> INSERT_SUBREG");
>> 
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA
>> G/InstrEmitter.h?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Thu Dec 13
>> +++ 00:34:11 2012
>> @@ -81,7 +81,7 @@
>>  /// supports SubIdx sub-registers.  Emit a copy if that isn't possible.
>>  /// Return the virtual register to use.
>>  unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
>> -                              EVT VT, DebugLoc DL);
>> +                              MVT VT, DebugLoc DL);
>> 
>>  /// EmitSubregNode - Generate machine code for subreg nodes.
>>  ///
>> 
>> Modified: 
>> llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA
>> G/ResourcePriorityQueue.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp Thu 
>> +++ Dec 13 00:34:11 2012
>> @@ -94,9 +94,9 @@
>>      continue;
>> 
>>    for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
>> -      EVT VT = ScegN->getValueType(i);
>> +      MVT VT = ScegN->getSimpleValueType(i);
>>      if (TLI->isTypeLegal(VT)
>> -         && (TLI->getRegClassFor(VT)->getID() == RCId)) {
>> +          && (TLI->getRegClassFor(VT)->getID() == RCId)) {
>>        NumberDeps++;
>>        break;
>>      }
>> @@ -132,9 +132,9 @@
>> 
>>    for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
>>      const SDValue &Op = ScegN->getOperand(i);
>> -      EVT VT = Op.getNode()->getValueType(Op.getResNo());
>> +      MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
>>      if (TLI->isTypeLegal(VT)
>> -         && (TLI->getRegClassFor(VT)->getID() == RCId)) {
>> +          && (TLI->getRegClassFor(VT)->getID() == RCId)) {
>>        NumberDeps++;
>>        break;
>>      }
>> @@ -332,7 +332,7 @@
>> 
>>  // Gen estimate.
>>  for (unsigned i = 0, e = SU->getNode()->getNumValues(); i != e; ++i) {
>> -      EVT VT = SU->getNode()->getValueType(i);
>> +      MVT VT = SU->getNode()->getSimpleValueType(i);
>>      if (TLI->isTypeLegal(VT)
>>          && TLI->getRegClassFor(VT)
>>          && TLI->getRegClassFor(VT)->getID() == RCId) @@ -341,7
>> +341,7 @@
>>  // Kill estimate.
>>  for (unsigned i = 0, e = SU->getNode()->getNumOperands(); i != e; ++i) {
>>      const SDValue &Op = SU->getNode()->getOperand(i);
>> -      EVT VT = Op.getNode()->getValueType(Op.getResNo());
>> +      MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
>>      if (isa<ConstantSDNode>(Op.getNode()))
>>        continue;
>> 
>> @@ -485,7 +485,7 @@
>>  if (ScegN->isMachineOpcode()) {
>>    // Estimate generated regs.
>>    for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
>> -      EVT VT = ScegN->getValueType(i);
>> +      MVT VT = ScegN->getSimpleValueType(i);
>> 
>>      if (TLI->isTypeLegal(VT)) {
>>        const TargetRegisterClass *RC = TLI->getRegClassFor(VT); @@
>> -496,7 +496,7 @@
>>    // Estimate killed regs.
>>    for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
>>      const SDValue &Op = ScegN->getOperand(i);
>> -      EVT VT = Op.getNode()->getValueType(Op.getResNo());
>> +      MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
>> 
>>      if (TLI->isTypeLegal(VT)) {
>>        const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
>> 
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA
>> G/SelectionDAGBuilder.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
>> (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu 
>> +++ Dec 13 00:34:11 2012
>> @@ -1760,8 +1760,8 @@
>>    Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
>>  }
>> 
>> -  B.RegVT = VT;
>> -  B.Reg = FuncInfo.CreateReg(VT);
>> +  B.RegVT = VT.getSimpleVT();
>> +  B.Reg = FuncInfo.CreateReg(B.RegVT.getSimpleVT());
>>  SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
>>                                    B.Reg, Sub);
>> 
>> @@ -6145,7 +6145,7 @@
>> 
>>          RegsForValue MatchedRegs;
>>          MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
>> -          EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
>> +          MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
>>          MatchedRegs.RegVTs.push_back(RegVT);
>>          MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
>>          for (unsigned i = 0, e =
>> InlineAsm::getNumOperandRegisters(OpFlag);
>> @@ -6683,8 +6683,8 @@
>>    // from the sret argument into it.
>>    SmallVector<EVT, 1> ValueVTs;
>>    ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
>> -    EVT VT = ValueVTs[0];
>> -    EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
>> +    MVT VT = ValueVTs[0].getSimpleVT();
>> +    MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(),
>> + VT).getSimpleVT();
>>    ISD::NodeType AssertOp = ISD::DELETED_NODE;
>>    SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
>>                                        RegVT, VT, NULL, AssertOp);
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastI
>> Sel.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Dec 13 00:34:11 2012
>> @@ -178,24 +178,24 @@
>>    bool isLoadTypeLegal(Type *Ty, MVT &VT);
>>    bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
>>                    bool isZExt);
>> -    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
>> +    bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
>>                     unsigned Alignment = 0, bool isZExt = true,
>>                     bool allocReg = true);
>> -    bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
>> +    bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
>>                      unsigned Alignment = 0);
>>    bool ARMComputeAddress(const Value *Obj, Address &Addr);
>>    void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
>>    bool ARMIsMemCpySmall(uint64_t Len);
>>    bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
>>                               unsigned Alignment);
>> -    unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
>> -    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
>> -    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
>> -    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
>> -    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
>> -    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
>> +    unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
>> +    unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
>> +    unsigned ARMMaterializeInt(const Constant *C, MVT VT);
>> +    unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
>> +    unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
>> +    unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
>>    unsigned ARMSelectCallOp(bool UseReg);
>> -    unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, EVT VT);
>> +    unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, 
>> + MVT VT);
>> 
>>    // Call handling routines.
>>  private:
>> @@ -487,7 +487,7 @@
>> 
>> // TODO: Don't worry about 64-bit now, but when this is fixed remove 
>> the // checks from the various callers.
>> -unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
>> +unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
>>  if (VT == MVT::f64) return 0;
>> 
>>  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
>> @@ -497,7 +497,7 @@
>>  return MoveReg;
>> }
>> 
>> -unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
>> +unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
>>  if (VT == MVT::i64) return 0;
>> 
>>  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
>> @@ -510,7 +510,7 @@
>> // For double width floating point we need to materialize two 
>> constants // (the high and the low) into integer registers then use a 
>> move to get // the combined constant into an FP reg.
>> -unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) 
>> {
>> +unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) 
>> +{
>>  const APFloat Val = CFP->getValueAPF();
>>  bool is64bit = VT == MVT::f64;
>> 
>> @@ -554,7 +554,7 @@
>>  return DestReg;
>> }
>> 
>> -unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
>> +unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
>> 
>>  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
>>    return false;
>> @@ -616,7 +616,7 @@
>>  return DestReg;
>> }
>> 
>> -unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) 
>> {
>> +unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) 
>> +{
>>  // For now 32-bit only.
>>  if (VT != MVT::i32) return 0;
>> 
>> @@ -719,10 +719,7 @@
>> }
>> 
>> unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
>> -  EVT VT = TLI.getValueType(C->getType(), true);
>> -
>> -  // Only handle simple types.
>> -  if (!VT.isSimple()) return 0;
>> +  MVT VT = TLI.getSimpleValueType(C->getType(), true);
> 
> Previously, this logic would fall back to selection dag isel if it encountered a non-simple VT.  Now if a non-simple VT is encountered it will assert.
> 
>>  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
>>    return ARMMaterializeFP(CFP, VT);
>> @@ -1003,14 +1000,13 @@
>>  AddOptionalDefs(MIB);
>> }
>> 
>> -bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address 
>> &Addr,
>> +bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address 
>> +&Addr,
>>                              unsigned Alignment, bool isZExt, bool
>> allocReg) {
>> -  assert(VT.isSimple() && "Non-simple types are invalid here!");
>>  unsigned Opc;
>>  bool useAM3 = false;
>>  bool needVMOV = false;
>>  const TargetRegisterClass *RC;
>> -  switch (VT.getSimpleVT().SimpleTy) {
>> +  switch (VT.SimpleTy) {
>>    // This is mostly going to be Neon/vector support.
>>    default: return false;
>>    case MVT::i1:
>> @@ -1127,11 +1123,11 @@
>>  return true;
>> }
>> 
>> -bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address 
>> &Addr,
>> +bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address 
>> +&Addr,
>>                               unsigned Alignment) {
>>  unsigned StrOpc;
>>  bool useAM3 = false;
>> -  switch (VT.getSimpleVT().SimpleTy) {
>> +  switch (VT.SimpleTy) {
>>    // This is mostly going to be Neon/vector support.
>>    default: return false;
>>    case MVT::i1: {
>> @@ -1405,8 +1401,7 @@
>> bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
>>                             bool isZExt) {
>>  Type *Ty = Src1Value->getType();
>> -  EVT SrcVT = TLI.getValueType(Ty, true);
>> -  if (!SrcVT.isSimple()) return false;
>> +  MVT SrcVT = TLI.getSimpleValueType(Ty, true);
> 
> Same.
> 
> For example,
> 
> define i32 @test(i31 %a, i31 %b) nounwind {
> entry:
>  %cmp = icmp ult i31 %a, %b
>  %conv2 = zext i1 %cmp to i32
>  ret i32 %conv2
> }
> 
> This will hit:
> Assertion failed: (isSimple() && "Expected a SimpleValueType!"), function getSimpleVT, file /Users/mcrosier/llvm-clean/llvm/include/llvm/CodeGen/ValueTypes.h, line 661.
> 
> Chad
> 
>>  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
>>  if (isFloat && !Subtarget->hasVFP2()) @@ -1443,7 +1438,7 @@
>>  unsigned CmpOpc;
>>  bool isICmp = true;
>>  bool needsExt = false;
>> -  switch (SrcVT.getSimpleVT().SimpleTy) {
>> +  switch (SrcVT.SimpleTy) {
>>    default: return false;
>>    // TODO: Verify compares.
>>    case MVT::f32:
>> @@ -1595,7 +1590,7 @@
>>    return false;
>> 
>>  Value *Src = I->getOperand(0);
>> -  EVT SrcVT = TLI.getValueType(Src->getType(), true);
>> +  MVT SrcVT = TLI.getSimpleValueType(Src->getType(), true);
>>  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
>>    return false;
>> 
>> @@ -1604,7 +1599,7 @@
>> 
>>  // Handle sign-extension.
>>  if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
>> -    EVT DestVT = MVT::i32;
>> +    MVT DestVT = MVT::i32;
>>    SrcReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT,
>>                                       /*isZExt*/!isSigned);
>>    if (SrcReg == 0) return false;
>> @@ -1811,7 +1806,7 @@
>> }
>> 
>> bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned
>> ISDOpcode) {
>> -  EVT VT  = TLI.getValueType(I->getType(), true);
>> +  MVT VT  = TLI.getSimpleValueType(I->getType(), true);
>> 
>>  // We can get here in the case when we want to use NEON for our fp
>>  // operations, but can't figure out how to. Just use the vfp 
>> instructions @@ -2055,7 +2050,7 @@
>>    if (RVLocs.size() == 2 && RetVT == MVT::f64) {
>>      // For this move we copy into two registers and then move into the
>>      // double fp reg we want.
>> -      EVT DestVT = RVLocs[0].getValVT();
>> +      MVT DestVT = RVLocs[0].getValVT();
>>      const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
>>      unsigned ResultReg = createResultReg(DstRC);
>>      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, @@
>> -2070,7 +2065,7 @@
>>      UpdateValueMap(I, ResultReg);
>>    } else {
>>      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
>> -      EVT CopyVT = RVLocs[0].getValVT();
>> +      MVT CopyVT = RVLocs[0].getValVT();
>> 
>>      // Special handling for extended integers.
>>      if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) 
>> @@ -2129,8 +2124,8 @@
>>      return false;
>> 
>>    unsigned SrcReg = Reg + VA.getValNo();
>> -    EVT RVVT = TLI.getValueType(RV->getType());
>> -    EVT DestVT = VA.getValVT();
>> +    MVT RVVT = TLI.getSimpleValueType(RV->getType());
>> +    MVT DestVT = VA.getValVT();
>>    // Special handling for extended integers.
>>    if (RVVT != DestVT) {
>>      if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) @@
>> -2175,7 +2170,7 @@ unsigned ARMFastISel::getLibcallReg(const Twine
>> &Name) {
>>  GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
>>                                       GlobalValue::ExternalLinkage, 
>> 0, Name);
>> -  return ARMMaterializeGV(GV, TLI.getValueType(GV->getType()));
>> +  return ARMMaterializeGV(GV, TLI.getSimpleValueType(GV->getType()));
>> }
>> 
>> // A quick function that will emit a call for a named libcall in F 
>> with the @@ -2587,7 +2582,7 @@
>>  return true;
>> }
>> 
>> -unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT 
>> DestVT,
>> +unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT 
>> +DestVT,
>>                                    bool isZExt) {
>>  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
>>    return 0;
>> @@ -2595,8 +2590,7 @@
>>  unsigned Opc;
>>  bool isBoolZext = false;
>>  const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
>> -  if (!SrcVT.isSimple()) return 0;
>> -  switch (SrcVT.getSimpleVT().SimpleTy) {
>> +  switch (SrcVT.SimpleTy) {
>>  default: return 0;
>>  case MVT::i16:
>>    if (!Subtarget->hasV6Ops()) return 0; @@ -2643,9 +2637,9 @@
>>  Value *Src = I->getOperand(0);
>>  Type *SrcTy = Src->getType();
>> 
>> -  EVT SrcVT, DestVT;
>> -  SrcVT = TLI.getValueType(SrcTy, true);
>> -  DestVT = TLI.getValueType(DestTy, true);
>> +  MVT SrcVT, DestVT;
>> +  SrcVT = TLI.getSimpleValueType(SrcTy, true);  DestVT = 
>> + TLI.getSimpleValueType(DestTy, true);
>> 
>>  bool isZExt = isa<ZExtInst>(I);
>>  unsigned SrcReg = getRegForValue(Src); @@ -2830,7 +2824,7 @@ }
>> 
>> unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
>> -                                     unsigned Align, EVT VT) {
>> +                                     unsigned Align, MVT VT) {
>>  bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
>>  ARMConstantPoolConstant *CPV =
>>    ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : 
>> ARMCP::GOT);
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelL
>> owering.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Dec 13 00:34:11
>> +++ 2012
>> @@ -1046,7 +1046,7 @@
>> 
>> /// getRegClassFor - Return the register class that should be used for 
>> the /// specified value type.
>> -const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) 
>> const {
>> +const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) 
>> +const {
>>  // Map v4i64 to QQ registers but do not make the type legal. Similarly map
>>  // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
>>  // load / store 4 to 8 consecutive D registers.
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelL
>> owering.h?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Dec 13 00:34:11
>> +++ 2012
>> @@ -367,7 +367,7 @@
>> 
>>    /// getRegClassFor - Return the register class that should be used for the
>>    /// specified value type.
>> -    virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
>> +    virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
>> 
>>    /// getMaximalGlobalOffset - Returns the maximal possible offset which can
>>    /// be used for loads / stores from the global.
>> 
>> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>> URL: 
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISe
>> lLowering.cpp?rev=170104&r1=170103&r2=170104&view=diff
>> ======================================================================
>> ========
>> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Dec 13
>> +++ 00:34:11 2012
>> @@ -2155,7 +2155,7 @@
>> 
>>  MachineFunction &MF = DAG.getMachineFunction();
>>  MachineFrameInfo *MFI = MF.getFrameInfo();
>> -  EVT VT = Op.getValueType();
>> +  MVT VT = Op.getSimpleValueType();
>>  unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
>>  MFI->setReturnAddressIsTaken(true);
>> 
>> @@ -3661,7 +3661,7 @@
>>    return;
>> 
>>  // Copy arg registers.
>> -  EVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
>> +  MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
>>  const TargetRegisterClass *RC = getRegClassFor(RegTy);
>> 
>>  for (unsigned I = 0; I < ByVal.NumRegs; ++I) { @@ -3783,7 +3783,7 @@
>>  const CCState &CCInfo = CC.getCCInfo();
>>  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
>>  unsigned RegSize = CC.regSize();
>> -  EVT RegTy = MVT::getIntegerVT(RegSize * 8);
>> +  MVT RegTy = MVT::getIntegerVT(RegSize * 8);
>>  const TargetRegisterClass *RC = getRegClassFor(RegTy);
>>  MachineFunction &MF = DAG.getMachineFunction();
>>  MachineFrameInfo *MFI = MF.getFrameInfo();
>> 
>> 
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