[llvm-commits] [llvm] r170342 - in /llvm/trunk/lib/Target/R600: AMDGPUMCInstLower.cpp AMDGPUMCInstLower.h MCTargetDesc/AMDGPUAsmBackend.cpp MCTargetDesc/SIMCCodeEmitter.cpp

[Tom Stellard]

Author: tstellar
Date: Mon Dec 17 09:14:54 2012
New Revision: 170342

URL: http://llvm.org/viewvc/llvm-project?rev=170342&view=rev
Log:
R600: BB operand support for SI

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Christian König <deathsimple at vodafone.de>

Modified:
    llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp
    llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h
    llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
    llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp?rev=170342&r1=170341&r2=170342&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp Mon Dec 17 09:14:54 2012
@@ -21,11 +21,14 @@
 #include "llvm/Constants.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCExpr.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
-AMDGPUMCInstLower::AMDGPUMCInstLower() { }
+AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
+  Ctx(ctx)
+{ }
 
 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(MI->getOpcode());
@@ -50,13 +53,16 @@
     case MachineOperand::MO_Register:
       MCOp = MCOperand::CreateReg(MO.getReg());
       break;
+    case MachineOperand::MO_MachineBasicBlock:
+      MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+                                   MO.getMBB()->getSymbol(), Ctx));
     }
     OutMI.addOperand(MCOp);
   }
 }
 
 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
-  AMDGPUMCInstLower MCInstLowering;
+  AMDGPUMCInstLower MCInstLowering(OutContext);
 
   if (MI->isBundle()) {
     const MachineBasicBlock *MBB = MI->getParent();

Modified: llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h?rev=170342&r1=170341&r2=170342&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.h Mon Dec 17 09:14:54 2012
@@ -14,12 +14,15 @@
 namespace llvm {
 
 class MCInst;
+class MCContext;
 class MachineInstr;
 
 class AMDGPUMCInstLower {
 
+  MCContext &Ctx;
+
 public:
-  AMDGPUMCInstLower();
+  AMDGPUMCInstLower(MCContext &ctx);
 
   /// \brief Lower a MachineInstr to an MCInst
   void lower(const MachineInstr *MI, MCInst &OutMI) const;

Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=170342&r1=170341&r2=170342&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp Mon Dec 17 09:14:54 2012
@@ -47,7 +47,7 @@
   virtual AMDGPUMCObjectWriter *createObjectWriter(raw_ostream &OS) const;
   virtual unsigned getNumFixupKinds() const { return 0; };
   virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                          uint64_t Value) const { assert(!"Not implemented"); }
+                          uint64_t Value) const;
   virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                                     const MCInstFragment *DF,
                                     const MCAsmLayout &Layout) const {
@@ -80,3 +80,11 @@
                                                         raw_ostream &OS) const {
   return new AMDGPUMCObjectWriter(OS);
 }
+
+void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
+                                  unsigned DataSize, uint64_t Value) const {
+
+  uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
+  assert(Fixup.getKind() == FK_PCRel_4);
+  *Dst = (Value - 4) / 4;
+}

Modified: llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp?rev=170342&r1=170341&r2=170342&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp Mon Dec 17 09:14:54 2012
@@ -21,6 +21,7 @@
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCFixup.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1))
@@ -149,6 +150,11 @@
     } Imm;
     Imm.F = MO.getFPImm();
     return Imm.I;
+  } else if (MO.isExpr()) {
+    const MCExpr *Expr = MO.getExpr();
+    MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
+    Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
+    return 0;
   } else{
     llvm_unreachable("Encoding of this operand type is not supported yet.");
   }