[llvm-commits] [llvm] r168735 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Chad Rosier]

Author: mcrosier
Date: Tue Nov 27 16:29:43 2012
New Revision: 168735

URL: http://llvm.org/viewvc/llvm-project?rev=168735&view=rev
Log:
[arm fast-isel] Appease the machine verifier by using the proper register
classes.  The vast majority of the remaining issues are due to uses of
invalid registers, which are defined by getRegForValue().  Those will be
a little more challenging to cleanup.
rdar://12719844

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=168735&r1=168734&r2=168735&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 27 16:29:43 2012
@@ -2586,26 +2586,24 @@
   default: return 0;
   case MVT::i16:
     if (!Subtarget->hasV6Ops()) return 0;
-    if (isZExt) {
+    RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+    if (isZExt)
       Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
-    } else {
+    else
       Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
-      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
-    }
     break;
   case MVT::i8:
     if (!Subtarget->hasV6Ops()) return 0;
-    if (isZExt) {
+    RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+    if (isZExt)
       Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
-    } else {
+    else
       Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
-      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
-    }
     break;
   case MVT::i1:
     if (isZExt) {
-      Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
+      Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
       isBoolZext = true;
       break;
     }