[llvm-commits] [llvm] r168728 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Chad Rosier]

Author: mcrosier
Date: Tue Nov 27 15:46:46 2012
New Revision: 168728

URL: http://llvm.org/viewvc/llvm-project?rev=168728&view=rev
Log:
[arm fast-isel] Appease the machine verifier by using the proper register
classes.  Also a bit of cleanup.
rdar://12719844

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=168728&r1=168727&r2=168728&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov 27 15:46:46 2012
@@ -1667,7 +1667,6 @@
 
   // Things need to be register sized for register moves.
   if (VT != MVT::i32) return false;
-  const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 
   unsigned CondReg = getRegForValue(I->getOperand(0));
   if (CondReg == 0) return false;
@@ -1700,14 +1699,16 @@
                   .addReg(CondReg).addImm(0));
 
   unsigned MovCCOpc;
+  const TargetRegisterClass *RC;
   if (!UseImm) {
+    RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
     MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
   } else {
-    if (!isNegativeImm) {
+    RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
+    if (!isNegativeImm)
       MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
-    } else {
+    else
       MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
-    }
   }
   unsigned ResultReg = createResultReg(RC);
   if (!UseImm)
@@ -2589,7 +2590,7 @@
       Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
     } else {
       Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
-      RC = isThumb2 ?&ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
     }
     break;
   case MVT::i8: