[llvm-commits] [llvm] r168657 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Chad Rosier]

Author: mcrosier
Date: Mon Nov 26 19:06:49 2012
New Revision: 168657

URL: http://llvm.org/viewvc/llvm-project?rev=168657&view=rev
Log:
[arm fast-isel] Appease the machine verifier by using the proper register
classes.  The associated test case still doesn't pass, but it does have far
fewer issues.
rdar://12719844

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=168657&r1=168656&r2=168657&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Nov 26 19:06:49 2012
@@ -563,7 +563,9 @@
   const ConstantInt *CI = cast<ConstantInt>(C);
   if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
     unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
-    unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
+    const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
+      &ARM::GPRRegClass;
+    unsigned ImmReg = createResultReg(RC);
     AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                             TII.get(Opc), ImmReg)
                     .addImm(CI->getZExtValue()));
@@ -2577,15 +2579,18 @@
 
   unsigned Opc;
   bool isBoolZext = false;
+  const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32);
   if (!SrcVT.isSimple()) return 0;
   switch (SrcVT.getSimpleVT().SimpleTy) {
   default: return 0;
   case MVT::i16:
     if (!Subtarget->hasV6Ops()) return 0;
-    if (isZExt)
+    if (isZExt) {
       Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
-    else
+    } else {
       Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
+      RC = isThumb2 ?&ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+    }
     break;
   case MVT::i8:
     if (!Subtarget->hasV6Ops()) return 0;
@@ -2597,13 +2602,14 @@
   case MVT::i1:
     if (isZExt) {
       Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
+      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
       isBoolZext = true;
       break;
     }
     return 0;
   }
 
-  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
+  unsigned ResultReg = createResultReg(RC);
   MachineInstrBuilder MIB;
   MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
         .addReg(SrcReg);