[llvm-commits] [PATCH] Add correct features for cortex-a15 in ARM.td

[Alex Rosenberg]

On Nov 19, 2012, at 1:56 AM, "Jiangning Liu" <jiangning.liu at arm.com> wrote:

> Hi,
>  
> This patch is to add correct features for ARM cortex-a15 processor.
>  
> Thanks,
> -Jiangning
>  
> diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
> index 23974ad..970a0b8 100644
> --- a/lib/Target/ARM/ARM.td
> +++ b/lib/Target/ARM/ARM.td
> @@ -149,10 +149,11 @@ def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
>                                      FeatureHWDivARM, FeatureAvoidPartialCPSR,
>                                      FeatureHasSlowFPVMLx]>;
>  
> -// FIXME: It has not been determined if A15 has these features.
>  def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
>                                     "Cortex-A15 ARM processors",
> -                                   [FeatureT2XtPk, FeatureFP16,
> +                                   [FeatureT2XtPk,
> +                                    FeatureNEONForFP, FeatureVFP4,
> +                                    FeatureHWDiv, FeatureHWDivARM,
>                                      FeatureAvoidPartialCPSR]>;
>  
>  class ProcNoItin<string Name, list<SubtargetFeature> Features>
> diff --git a/test/CodeGen/ARM/a15-fpv4.ll b/test/CodeGen/ARM/a15-fpv4.ll
> new file mode 100644
> index 0000000..94bb878
> --- /dev/null
> +++ b/test/CodeGen/ARM/a15-fpv4.ll
> @@ -0,0 +1,22 @@
> +; RUN: llc < %s -mcpu=cortex-a15 | FileCheck %s
> +
> +; This test checks that the fpv4 feature is enabled for A15.

vfp4

Alex

> +
> +; CHECK: test_fma
> +; CHECK: vfma.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
> +define float @test_fma(float %a, float %b, float %c) {
> +  %res = call float @llvm.fma.f32(float %a, float %b, float %c) nounwind
> +
> +  ret float %res
> +}
> +
> +; CHECK: test_fma_d
> +; CHECK: vfma.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
> +define double @test_fma_d(double %a, double %b, double %c) {
> +  %res = call double @llvm.fma.f64(double %a, double %b, double %c) nounwind
> +
> +  ret double %res
> +}
> +
> +declare float @llvm.fma.f32(float, float, float) nounwind readnone
> +declare double @llvm.fma.f64(double, double, double) nounwind readnone
> diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll
> index 82cfca1..f0f93d4 100644
> --- a/test/CodeGen/ARM/div.ll
> +++ b/test/CodeGen/ARM/div.ll
> @@ -1,5 +1,7 @@
>  ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM
>  ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift     | FileCheck %s -check-prefix=CHECK-SWIFT
> +; RUN: llc < %s -march=arm -mcpu=cortex-a15            | FileCheck %s -check-prefix=CHECK-A15
> +; RUN: llc < %s -march=thumb -mcpu=cortex-a15          | FileCheck %s -check-prefix=CHECK-A15
>  
>  define i32 @f1(i32 %a, i32 %b) {
>  entry:
> @@ -8,6 +10,9 @@ entry:
>  
>  ; CHECK-SWIFT: f1
>  ; CHECK-SWIFT: sdiv
> +
> +; CHECK-A15: f1
> +; CHECK-A15: sdiv
>          %tmp1 = sdiv i32 %a, %b         ; <i32> [#uses=1]
>          ret i32 %tmp1
>  }
> @@ -19,6 +24,9 @@ entry:
>  
>  ; CHECK-SWIFT: f2
>  ; CHECK-SWIFT: udiv
> +
> +; CHECK-A15: f2
> +; CHECK-A15: udiv
>          %tmp1 = udiv i32 %a, %b         ; <i32> [#uses=1]
>          ret i32 %tmp1
>  }
> @@ -31,6 +39,10 @@ entry:
>  ; CHECK-SWIFT: f3
>  ; CHECK-SWIFT: sdiv
>  ; CHECK-SWIFT: mls
> +
> +; CHECK-A15: f3
> +; CHECK-A15: sdiv
> +; CHECK-A15: mls
>          %tmp1 = srem i32 %a, %b         ; <i32> [#uses=1]
>          ret i32 %tmp1
>  }
> @@ -43,6 +55,10 @@ entry:
>  ; CHECK-SWIFT: f4
>  ; CHECK-SWIFT: udiv
>  ; CHECK-SWIFT: mls
> +
> +; CHECK-A15: f4
> +; CHECK-A15: udiv
> +; CHECK-A15: mls
>          %tmp1 = urem i32 %a, %b         ; <i32> [#uses=1]
>          ret i32 %tmp1
>  }
> diff --git a/test/CodeGen/ARM/neon-fma.ll b/test/CodeGen/ARM/neon-fma.ll
> index d2cca50..b9e23b2 100644
> --- a/test/CodeGen/ARM/neon-fma.ll
> +++ b/test/CodeGen/ARM/neon-fma.ll
> @@ -1,4 +1,5 @@
>  ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=swift | FileCheck %s
> +; RUN: llc < %s -mcpu=cortex-a15 | FileCheck %s
>  
>  ; CHECK: test_v2f32
>  ; CHECK: vfma.f32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
> 
> 
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