[llvm-commits] [llvm] r168320 - in /llvm/trunk: lib/CodeGen/LiveInterval.cpp test/CodeGen/X86/inline-asm.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Mon Nov 19 13:31:10 2012
New Revision: 168320

URL: http://llvm.org/viewvc/llvm-project?rev=168320&view=rev
Log:
Handle mixed normal and early-clobber defs on inline asm.

PR14376.

Modified:
    llvm/trunk/lib/CodeGen/LiveInterval.cpp
    llvm/trunk/test/CodeGen/X86/inline-asm.ll

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=168320&r1=168319&r2=168320&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Mon Nov 19 13:31:10 2012
@@ -59,8 +59,16 @@
     return VNI;
   }
   if (SlotIndex::isSameInstr(Def, I->start)) {
-    assert(I->start == Def && "Cannot insert def, already live");
-    assert(I->valno->def == Def && "Inconsistent existing value def");
+    assert(I->valno->def == I->start && "Inconsistent existing value def");
+
+    // It is possible to have both normal and early-clobber defs of the same
+    // register on an instruction. It doesn't make a lot of sense, but it is
+    // possible to specify in inline assembly.
+    //
+    // Just convert everything to early-clobber.
+    Def = std::min(Def, I->start);
+    if (Def != I->start)
+      I->start = I->valno->def = Def;
     return I->valno;
   }
   assert(SlotIndex::isEarlierInstr(Def, I->start) && "Already live at def");

Modified: llvm/trunk/test/CodeGen/X86/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm.ll?rev=168320&r1=168319&r2=168320&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm.ll Mon Nov 19 13:31:10 2012
@@ -52,3 +52,10 @@
   %0 = call { i32, i32, i32, i32, i32 } asm sideeffect "", "=&r,=&r,=&r,=&r,=&q,r,~{ecx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %h) nounwind
   ret void
 }
+
+; Mix normal and EC defs of the same register.
+define i32 @pr14376() nounwind noinline {
+entry:
+  %asm = tail call i32 asm sideeffect "", "={ax},i,~{eax},~{flags},~{rax}"(i64 61) nounwind
+  ret i32 %asm
+}