[llvm-commits] [llvm] r168131 - in /llvm/trunk: lib/Target/Mips/MipsDelaySlotFiller.cpp test/CodeGen/Mips/brdelayslot.ll

[Akira Hatanaka]

Author: ahatanak
Date: Thu Nov 15 20:39:34 2012
New Revision: 168131

URL: http://llvm.org/viewvc/llvm-project?rev=168131&view=rev
Log:
[mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot.

Modified:
    llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
    llvm/trunk/test/CodeGen/Mips/brdelayslot.ll

Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=168131&r1=168130&r2=168131&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Thu Nov 15 20:39:34 2012
@@ -231,31 +231,48 @@
   return false;
 }
 
+// Helper function for getting a MachineOperand's register number and adding it
+// to RegDefs or RegUses.
+static void insertDefUse(const MachineOperand &MO,
+                         SmallSet<unsigned, 32> &RegDefs,
+                         SmallSet<unsigned, 32> &RegUses,
+                         unsigned ExcludedReg = 0) {
+  unsigned Reg;
+
+  if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
+    return;
+
+  if (MO.isDef())
+    RegDefs.insert(Reg);
+  else if (MO.isUse())
+    RegUses.insert(Reg);
+}
+
 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
 void Filler::insertDefsUses(InstrIter MI,
                             SmallSet<unsigned, 32> &RegDefs,
                             SmallSet<unsigned, 32> &RegUses) {
-  // If MI is a call or return, just examine the explicit non-variadic operands.
-  MCInstrDesc MCID = MI->getDesc();
-  unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
-                                                MI->getNumOperands();
+  unsigned I, E = MI->getDesc().getNumOperands();
 
-  // Add RA to RegDefs to prevent users of RA from going into delay slot.
-  if (MI->isCall())
-    RegDefs.insert(Mips::RA);
+  for (I = 0; I != E; ++I)
+    insertDefUse(MI->getOperand(I), RegDefs, RegUses);
 
-  for (unsigned i = 0; i != e; ++i) {
-    const MachineOperand &MO = MI->getOperand(i);
-    unsigned Reg;
-
-    if (!MO.isReg() || !(Reg = MO.getReg()))
-      continue;
-
-    if (MO.isDef())
-      RegDefs.insert(Reg);
-    else if (MO.isUse())
-      RegUses.insert(Reg);
+  // If MI is a call, add RA to RegDefs to prevent users of RA from going into
+  // delay slot.
+  if (MI->isCall()) {
+    RegDefs.insert(Mips::RA);
+    return;
   }
+
+  // Return if MI is a return.
+  if (MI->isReturn())
+    return;
+
+  // Examine the implicit operands. Exclude register AT which is in the list of
+  // clobbered registers of branch instructions.
+  E = MI->getNumOperands();
+  for (; I != E; ++I)
+    insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
 }
 
 //returns true if the Reg or its alias is in the RegSet.

Modified: llvm/trunk/test/CodeGen/Mips/brdelayslot.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/brdelayslot.ll?rev=168131&r1=168130&r2=168131&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/brdelayslot.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/brdelayslot.ll Thu Nov 15 20:39:34 2012
@@ -35,3 +35,35 @@
 
 declare void @foo4(double)
 
+ at g2 = external global i32
+ at g1 = external global i32
+ at g3 = external global i32
+
+; Check that branch delay slot can be filled with an instruction with operand
+; $1.
+;
+; Default:     foo5:
+; Default-NOT: nop
+
+define void @foo5(i32 %a) nounwind {
+entry:
+  %0 = load i32* @g2, align 4
+  %tobool = icmp eq i32 %a, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:
+  %1 = load i32* @g1, align 4
+  %add = add nsw i32 %1, %0
+  store i32 %add, i32* @g1, align 4
+  br label %if.end
+
+if.else:
+  %2 = load i32* @g3, align 4
+  %sub = sub nsw i32 %2, %0
+  store i32 %sub, i32* @g3, align 4
+  br label %if.end
+
+if.end:
+  ret void
+}
+