[llvm-commits] [Clang] Clean up and fix X86 CPU features

Sean Silva silvas at purdue.edu
Thu Nov 15 09:59:31 PST 2012


My bad. I pointed Jung-uk Kim to llvm-commits. Honestly I didn't look
into the patch; I just saw "X86 CPU features" and assumed it was a
patch for LLVM and not Clang for some reason.

On Thu, Nov 15, 2012 at 2:11 AM, Craig Topper <craig.topper at gmail.com> wrote:
> Also this mail went to the wrong list. You want clang-commits.
>
>
> On Wed, Nov 14, 2012 at 11:10 PM, Craig Topper <craig.topper at gmail.com>
> wrote:
>>
>> I'd rather not enable CLMUL and AES with AVX. The current behavior was
>> consistent with gcc.
>>
>> On Wed, Nov 14, 2012 at 4:09 PM, Jung-uk Kim <jkim at freebsd.org> wrote:
>>>
>>> -----BEGIN PGP SIGNED MESSAGE-----
>>> Hash: SHA1
>>>
>>> [Copied from PR14344 and edited for Sean Silva <silvas at purdue.edu>]
>>>
>>> I have an AMD Family 10h processor and I realized that LZCNT and
>>> POPCNT are not enabled by default.  Then, I looked at clang's
>>> lib/Basic/Targets.cpp and found it needs some love. :-)
>>>
>>> Please see the attached patch.
>>>
>>> - - AMD SSE4A capable processors have LZCNT, POPCNT, and SSE3
>>> instructions.
>>> - - AMD Piledriver("bdver2") processors have BMI and FMA instructions.
>>> - - All SSE levels enable MMX by default.
>>> - - All AVX capable processors have AES and PCLMUL instructions.
>>> - - Sync. F16C feature with LLVM's X86.td.
>>>
>>> Thanks!
>>>
>>> Jung-uk Kim
>>> -----BEGIN PGP SIGNATURE-----
>>> Version: GnuPG v2.0.19 (FreeBSD)
>>> Comment: Using GnuPG with Mozilla - http://www.enigmail.net/
>>>
>>> iEYEARECAAYFAlCkMtYACgkQmlay1b9qnVOCvQCffcRSkdryJb5YD5v0s7NyFJF+
>>> eQgAoNE/TIapwuTXMQD9mfljX4L8x32g
>>> =RIA0
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>>>
>>> _______________________________________________
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>>> llvm-commits at cs.uiuc.edu
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>>>
>>
>>
>>
>> --
>> ~Craig
>
>
>
>
> --
> ~Craig
>
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