[llvm-commits] [llvm] r167984 - in /llvm/trunk: autoconf/configure.ac configure docs/CodeGenerator.rst include/llvm/ADT/Triple.h include/llvm/Intrinsics.td include/llvm/IntrinsicsCellSPU.td lib/Support/Triple.cpp lib/Target/CellSPU/ lib/Target/LLVMBuild.txt test/CodeGen/CellSPU/ utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
Eric Christopher
echristo at gmail.com
Wed Nov 14 14:09:20 PST 2012
Author: echristo
Date: Wed Nov 14 16:09:20 2012
New Revision: 167984
URL: http://llvm.org/viewvc/llvm-project?rev=167984&view=rev
Log:
Remove the CellSPU port.
Approved by Chris Lattner.
Removed:
llvm/trunk/include/llvm/IntrinsicsCellSPU.td
llvm/trunk/lib/Target/CellSPU/
llvm/trunk/test/CodeGen/CellSPU/
Modified:
llvm/trunk/autoconf/configure.ac
llvm/trunk/configure
llvm/trunk/docs/CodeGenerator.rst
llvm/trunk/include/llvm/ADT/Triple.h
llvm/trunk/include/llvm/Intrinsics.td
llvm/trunk/lib/Support/Triple.cpp
llvm/trunk/lib/Target/LLVMBuild.txt
llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Wed Nov 14 16:09:20 2012
@@ -697,14 +697,14 @@
TARGETS_TO_BUILD=""
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all or target1,target2,... Valid targets are:
- host, x86, x86_64, sparc, powerpc, arm, mips, spu, hexagon,
+ host, x86, x86_64, sparc, powerpc, arm, mips, hexagon,
xcore, msp430, nvptx, and cpp (default=all)]),,
enableval=all)
if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -716,7 +716,6 @@
mipsel) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64el) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
- spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -731,7 +730,6 @@
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
- CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Wed Nov 14 16:09:20 2012
@@ -1426,8 +1426,8 @@
YES)
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
- x86_64, sparc, powerpc, arm, mips, spu, hexagon,
- xcore, msp430, nvptx, and cpp (default=all)
+ x86_64, sparc, powerpc, arm, mips, hexagon, xcore,
+ msp430, nvptx, and cpp (default=all)
--enable-experimental-targets
Build experimental host targets: disable or
target1,target2,... (default=disable)
@@ -5418,7 +5418,7 @@
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5430,7 +5430,6 @@
mipsel) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64el) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
- spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -5445,7 +5444,6 @@
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
- CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
@@ -10315,7 +10313,7 @@
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
-#line 10318 "configure"
+#line 10316 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
Modified: llvm/trunk/docs/CodeGenerator.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.rst?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/docs/CodeGenerator.rst (original)
+++ llvm/trunk/docs/CodeGenerator.rst Wed Nov 14 16:09:20 2012
@@ -1762,7 +1762,6 @@
:raw-html:`<tr>`
:raw-html:`<th>Feature</th>`
:raw-html:`<th>ARM</th>`
-:raw-html:`<th>CellSPU</th>`
:raw-html:`<th>Hexagon</th>`
:raw-html:`<th>MBlaze</th>`
:raw-html:`<th>MSP430</th>`
@@ -1777,7 +1776,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a href="#feat_reliable">is generally reliable</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
@@ -1792,7 +1790,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a href="#feat_asmparser">assembly parser</a></td>`
:raw-html:`<td class="no"></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
@@ -1807,7 +1804,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a href="#feat_disassembler">disassembler</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
@@ -1822,7 +1818,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a href="#feat_inlineasm">inline asm</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
@@ -1837,7 +1832,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a href="#feat_jit">jit</a></td>`
:raw-html:`<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
@@ -1852,7 +1846,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a href="#feat_objectwrite">.o file writing</a></td>`
:raw-html:`<td class="no"></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="yes"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
@@ -1867,7 +1860,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a hr:raw-html:`ef="#feat_tailcall">tail calls</a></td>`
:raw-html:`<td class="yes"></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="yes"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="unknown"></td> <!-- MSP430 -->`
@@ -1882,7 +1874,6 @@
:raw-html:`<tr>`
:raw-html:`<td><a href="#feat_segstacks">segmented stacks</a></td>`
:raw-html:`<td class="no"></td> <!-- ARM -->`
-:raw-html:`<td class="no"></td> <!-- CellSPU -->`
:raw-html:`<td class="no"></td> <!-- Hexagon -->`
:raw-html:`<td class="no"></td> <!-- MBlaze -->`
:raw-html:`<td class="no"></td> <!-- MSP430 -->`
Modified: llvm/trunk/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/Triple.h (original)
+++ llvm/trunk/include/llvm/ADT/Triple.h Wed Nov 14 16:09:20 2012
@@ -44,7 +44,6 @@
UnknownArch,
arm, // ARM; arm, armv.*, xscale
- cellspu, // CellSPU: spu, cellspu
hexagon, // Hexagon: hexagon
mips, // MIPS: mips, mipsallegrex
mipsel, // MIPSEL: mipsel, mipsallegrexel
Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Wed Nov 14 16:09:20 2012
@@ -464,7 +464,6 @@
include "llvm/IntrinsicsPowerPC.td"
include "llvm/IntrinsicsX86.td"
include "llvm/IntrinsicsARM.td"
-include "llvm/IntrinsicsCellSPU.td"
include "llvm/IntrinsicsXCore.td"
include "llvm/IntrinsicsHexagon.td"
include "llvm/IntrinsicsNVVM.td"
Removed: llvm/trunk/include/llvm/IntrinsicsCellSPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsCellSPU.td?rev=167983&view=auto
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsCellSPU.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsCellSPU.td (removed)
@@ -1,242 +0,0 @@
-//==- IntrinsicsCellSPU.td - Cell SDK intrinsics -*- tablegen -*-==//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// Department at The Aerospace Corporation and is distributed under the
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// Cell SPU Instructions:
-//===----------------------------------------------------------------------===//
-// TODO Items (not urgent today, but would be nice, low priority)
-//
-// ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
-// concatenating the byte argument b as "bbbb". Could recognize this bit pattern
-// in 16-bit and 32-bit constants and reduce instruction count.
-//===----------------------------------------------------------------------===//
-
-// 7-bit integer type, used as an immediate:
-def cell_i7_ty: LLVMType<i8>;
-def cell_i8_ty: LLVMType<i8>;
-
-// Keep this here until it's actually supported:
-def llvm_i128_ty : LLVMType<i128>;
-
-class v16i8_u7imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, cell_i7_ty],
- [IntrNoMem]>;
-
-class v16i8_u8imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i8_ty],
- [IntrNoMem]>;
-
-class v16i8_s10imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i16_ty],
- [IntrNoMem]>;
-
-class v16i8_u16imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i16_ty],
- [IntrNoMem]>;
-
-class v16i8_rr<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
- [IntrNoMem]>;
-
-class v8i16_s10imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i16_ty],
- [IntrNoMem]>;
-
-class v8i16_u16imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i16_ty],
- [IntrNoMem]>;
-
-class v8i16_rr<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
-
-class v4i32_rr<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- [IntrNoMem]>;
-
-class v4i32_u7imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, cell_i7_ty],
- [IntrNoMem]>;
-
-class v4i32_s10imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i16_ty],
- [IntrNoMem]>;
-
-class v4i32_u16imm<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i16_ty],
- [IntrNoMem]>;
-
-class v4f32_rr<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
- [IntrNoMem]>;
-
-class v4f32_rrr<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
- [IntrNoMem]>;
-
-class v2f64_rr<string builtin_suffix> :
- GCCBuiltin<!strconcat("__builtin_si_", builtin_suffix)>,
- Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty],
- [IntrNoMem]>;
-
-// All Cell SPU intrinsics start with "llvm.spu.".
-let TargetPrefix = "spu" in {
- def int_spu_si_fsmbi : v8i16_u16imm<"fsmbi">;
- def int_spu_si_ah : v8i16_rr<"ah">;
- def int_spu_si_ahi : v8i16_s10imm<"ahi">;
- def int_spu_si_a : v4i32_rr<"a">;
- def int_spu_si_ai : v4i32_s10imm<"ai">;
- def int_spu_si_sfh : v8i16_rr<"sfh">;
- def int_spu_si_sfhi : v8i16_s10imm<"sfhi">;
- def int_spu_si_sf : v4i32_rr<"sf">;
- def int_spu_si_sfi : v4i32_s10imm<"sfi">;
- def int_spu_si_addx : v4i32_rr<"addx">;
- def int_spu_si_cg : v4i32_rr<"cg">;
- def int_spu_si_cgx : v4i32_rr<"cgx">;
- def int_spu_si_sfx : v4i32_rr<"sfx">;
- def int_spu_si_bg : v4i32_rr<"bg">;
- def int_spu_si_bgx : v4i32_rr<"bgx">;
- def int_spu_si_mpy : // This is special:
- GCCBuiltin<"__builtin_si_mpy">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyu : // This is special:
- GCCBuiltin<"__builtin_si_mpyu">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyi : // This is special:
- GCCBuiltin<"__builtin_si_mpyi">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyui : // This is special:
- GCCBuiltin<"__builtin_si_mpyui">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpya : // This is special:
- GCCBuiltin<"__builtin_si_mpya">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyh : // This is special:
- GCCBuiltin<"__builtin_si_mpyh">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpys : // This is special:
- GCCBuiltin<"__builtin_si_mpys">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyhh : // This is special:
- GCCBuiltin<"__builtin_si_mpyhh">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyhha : // This is special:
- GCCBuiltin<"__builtin_si_mpyhha">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyhhu : // This is special:
- GCCBuiltin<"__builtin_si_mpyhhu">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
- def int_spu_si_mpyhhau : // This is special:
- GCCBuiltin<"__builtin_si_mpyhhau">,
- Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
- [IntrNoMem]>;
-
- def int_spu_si_shli: v4i32_u7imm<"shli">;
-
- def int_spu_si_shlqbi:
- GCCBuiltin<!strconcat("__builtin_si_", "shlqbi")>,
- Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty],
- [IntrNoMem]>;
-
- def int_spu_si_shlqbii: v16i8_u7imm<"shlqbii">;
- def int_spu_si_shlqby:
- GCCBuiltin<!strconcat("__builtin_si_", "shlqby")>,
- Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty],
- [IntrNoMem]>;
- def int_spu_si_shlqbyi: v16i8_u7imm<"shlqbyi">;
-
- def int_spu_si_ceq: v4i32_rr<"ceq">;
- def int_spu_si_ceqi: v4i32_s10imm<"ceqi">;
- def int_spu_si_ceqb: v16i8_rr<"ceqb">;
- def int_spu_si_ceqbi: v16i8_u8imm<"ceqbi">;
- def int_spu_si_ceqh: v8i16_rr<"ceqh">;
- def int_spu_si_ceqhi: v8i16_s10imm<"ceqhi">;
- def int_spu_si_cgt: v4i32_rr<"cgt">;
- def int_spu_si_cgti: v4i32_s10imm<"cgti">;
- def int_spu_si_cgtb: v16i8_rr<"cgtb">;
- def int_spu_si_cgtbi: v16i8_u8imm<"cgtbi">;
- def int_spu_si_cgth: v8i16_rr<"cgth">;
- def int_spu_si_cgthi: v8i16_s10imm<"cgthi">;
- def int_spu_si_clgtb: v16i8_rr<"clgtb">;
- def int_spu_si_clgtbi: v16i8_u8imm<"clgtbi">;
- def int_spu_si_clgth: v8i16_rr<"clgth">;
- def int_spu_si_clgthi: v8i16_s10imm<"clgthi">;
- def int_spu_si_clgt: v4i32_rr<"clgt">;
- def int_spu_si_clgti: v4i32_s10imm<"clgti">;
-
- def int_spu_si_and: v4i32_rr<"and">;
- def int_spu_si_andbi: v16i8_u8imm<"andbi">;
- def int_spu_si_andc: v4i32_rr<"andc">;
- def int_spu_si_andhi: v8i16_s10imm<"andhi">;
- def int_spu_si_andi: v4i32_s10imm<"andi">;
-
- def int_spu_si_or: v4i32_rr<"or">;
- def int_spu_si_orbi: v16i8_u8imm<"orbi">;
- def int_spu_si_orc: v4i32_rr<"orc">;
- def int_spu_si_orhi: v8i16_s10imm<"orhi">;
- def int_spu_si_ori: v4i32_s10imm<"ori">;
-
- def int_spu_si_xor: v4i32_rr<"xor">;
- def int_spu_si_xorbi: v16i8_u8imm<"xorbi">;
- def int_spu_si_xorhi: v8i16_s10imm<"xorhi">;
- def int_spu_si_xori: v4i32_s10imm<"xori">;
-
- def int_spu_si_nor: v4i32_rr<"nor">;
- def int_spu_si_nand: v4i32_rr<"nand">;
-
- def int_spu_si_fa: v4f32_rr<"fa">;
- def int_spu_si_fs: v4f32_rr<"fs">;
- def int_spu_si_fm: v4f32_rr<"fm">;
-
- def int_spu_si_fceq: v4f32_rr<"fceq">;
- def int_spu_si_fcmeq: v4f32_rr<"fcmeq">;
- def int_spu_si_fcgt: v4f32_rr<"fcgt">;
- def int_spu_si_fcmgt: v4f32_rr<"fcmgt">;
-
- def int_spu_si_fma: v4f32_rrr<"fma">;
- def int_spu_si_fnms: v4f32_rrr<"fnms">;
- def int_spu_si_fms: v4f32_rrr<"fms">;
-
- def int_spu_si_dfa: v2f64_rr<"dfa">;
- def int_spu_si_dfs: v2f64_rr<"dfs">;
- def int_spu_si_dfm: v2f64_rr<"dfm">;
-
-//def int_spu_si_dfceq: v2f64_rr<"dfceq">;
-//def int_spu_si_dfcmeq: v2f64_rr<"dfcmeq">;
-//def int_spu_si_dfcgt: v2f64_rr<"dfcgt">;
-//def int_spu_si_dfcmgt: v2f64_rr<"dfcmgt">;
-
- def int_spu_si_dfnma: v2f64_rr<"dfnma">;
- def int_spu_si_dfma: v2f64_rr<"dfma">;
- def int_spu_si_dfnms: v2f64_rr<"dfnms">;
- def int_spu_si_dfms: v2f64_rr<"dfms">;
-}
Modified: llvm/trunk/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Triple.cpp (original)
+++ llvm/trunk/lib/Support/Triple.cpp Wed Nov 14 16:09:20 2012
@@ -20,7 +20,6 @@
case UnknownArch: return "unknown";
case arm: return "arm";
- case cellspu: return "cellspu";
case hexagon: return "hexagon";
case mips: return "mips";
case mipsel: return "mipsel";
@@ -56,8 +55,6 @@
case arm:
case thumb: return "arm";
- case cellspu: return "spu";
-
case ppc64:
case ppc: return "ppc";
@@ -153,7 +150,6 @@
Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
return StringSwitch<Triple::ArchType>(Name)
.Case("arm", arm)
- .Case("cellspu", cellspu)
.Case("mips", mips)
.Case("mipsel", mipsel)
.Case("mips64", mips64)
@@ -220,7 +216,6 @@
.StartsWith("armv", Triple::arm)
.Case("thumb", Triple::thumb)
.StartsWith("thumbv", Triple::thumb)
- .Cases("spu", "cellspu", Triple::cellspu)
.Case("msp430", Triple::msp430)
.Cases("mips", "mipseb", "mipsallegrex", Triple::mips)
.Cases("mipsel", "mipsallegrexel", Triple::mipsel)
@@ -659,7 +654,6 @@
case llvm::Triple::amdil:
case llvm::Triple::arm:
- case llvm::Triple::cellspu:
case llvm::Triple::hexagon:
case llvm::Triple::le32:
case llvm::Triple::mblaze:
@@ -709,7 +703,6 @@
case Triple::amdil:
case Triple::spir:
case Triple::arm:
- case Triple::cellspu:
case Triple::hexagon:
case Triple::le32:
case Triple::mblaze:
@@ -742,7 +735,6 @@
case Triple::UnknownArch:
case Triple::amdil:
case Triple::arm:
- case Triple::cellspu:
case Triple::hexagon:
case Triple::le32:
case Triple::mblaze:
Modified: llvm/trunk/lib/Target/LLVMBuild.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/lib/Target/LLVMBuild.txt (original)
+++ llvm/trunk/lib/Target/LLVMBuild.txt Wed Nov 14 16:09:20 2012
@@ -16,7 +16,7 @@
;===------------------------------------------------------------------------===;
[common]
-subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC Sparc X86 XCore
+subdirectories = ARM CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC Sparc X86 XCore
; This is a special group whose required libraries are extended (by llvm-build)
; with the best execution engine (the native JIT, if available, or the
Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp Wed Nov 14 16:09:20 2012
@@ -2,7 +2,7 @@
# Do not edit here. If you wish to override these values
# edit the last section
set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips PIC16 XCore MSP430 Blackfin MSIL CppBackend"
set srcroot "/Volumes/Data/ddunbar/llvm"
set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
set srcdir "/Volumes/Data/ddunbar/llvm/test"
Modified: llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp?rev=167984&r1=167983&r2=167984&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp (original)
+++ llvm/trunk/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp Wed Nov 14 16:09:20 2012
@@ -2,7 +2,7 @@
# Do not edit here. If you wish to override these values
# edit the last section
set target_triplet "x86_64-apple-darwin10"
-set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips CellSPU PIC16 XCore MSP430 Blackfin MSIL CppBackend"
+set TARGETS_TO_BUILD "X86 Sparc PowerPC ARM Mips PIC16 XCore MSP430 Blackfin MSIL CppBackend"
set srcroot "/Volumes/Data/ddunbar/llvm"
set objroot "/Volumes/Data/ddunbar/llvm.obj.64"
set srcdir "/Volumes/Data/ddunbar/llvm/test"
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