[llvm-commits] [llvm] r167862 - in /llvm/trunk/lib/Target/PowerPC: PPCInstrFormats.td PPCInstrInfo.td

[Chandler Carruth]

On Tue, Nov 13, 2012 at 11:19 AM, Ulrich Weigand
<ulrich.weigand at de.ibm.com> wrote:
> Author: uweigand
> Date: Tue Nov 13 13:19:46 2012
> New Revision: 167862
>
> URL: http://llvm.org/viewvc/llvm-project?rev=167862&view=rev
> Log:
> Fix wrong PowerPC instruction encodings due to
> operand field name mismatches in:
>  - AForm_3  (fmul, fmuls)
>  - XFXForm_5 (mtcrf)
>  - XFLForm (mtfsf)

Second patch without any test cases!

>
> Modified:
>     llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
>     llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td?rev=167862&r1=167861&r2=167862&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrFormats.td Tue Nov 13 13:19:46 2012
> @@ -626,9 +626,9 @@
>                  InstrItinClass itin>
>    : I<opcode, OOL, IOL, asmstr, itin> {
>    bits<8>  FXM;
> -  bits<5>  ST;
> +  bits<5>  rS;
>
> -  let Inst{6-10}  = ST;
> +  let Inst{6-10}  = rS;
>    let Inst{11}    = 0;
>    let Inst{12-19} = FXM;
>    let Inst{20}    = 0;
> @@ -667,7 +667,7 @@
>                        string cstr, InstrItinClass itin, list<dag>pattern>
>    : I<opcode, OOL, IOL, asmstr, itin> {
>    bits<8> FM;
> -  bits<5> RT;
> +  bits<5> rT;
>
>    bit RC = 0;    // set by isDOT
>    let Pattern = pattern;
> @@ -676,7 +676,7 @@
>    let Inst{6} = 0;
>    let Inst{7-14}  = FM;
>    let Inst{15} = 0;
> -  let Inst{16-20} = RT;
> +  let Inst{16-20} = rT;
>    let Inst{21-30} = xo;
>    let Inst{31}    = RC;
>  }
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=167862&r1=167861&r2=167862&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 13 13:19:46 2012
> @@ -1395,13 +1395,13 @@
>                        "fdivs $FRT, $FRA, $FRB", FPDivS,
>                        [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
>    def FMUL  : AForm_3<63, 25,
> -                      (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
> -                      "fmul $FRT, $FRA, $FRB", FPFused,
> -                      [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
> +                      (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
> +                      "fmul $FRT, $FRA, $FRC", FPFused,
> +                      [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRC))]>;
>    def FMULS : AForm_3<59, 25,
> -                      (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
> -                      "fmuls $FRT, $FRA, $FRB", FPGeneral,
> -                      [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
> +                      (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
> +                      "fmuls $FRT, $FRA, $FRC", FPGeneral,
> +                      [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRC))]>;
>    def FSUB  : AForm_2<63, 20,
>                        (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
>                        "fsub $FRT, $FRA, $FRB", FPAddSub,
>
>
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