[llvm-commits] [llvm] r167718 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2010-01-08-Atomic64Bug.ll test/CodeGen/X86/pr14314.ll

[Eli Friedman]

On Sun, Nov 11, 2012 at 10:49 PM, Michael Liao <michael.liao at intel.com> wrote:
> Author: hliao
> Date: Mon Nov 12 00:49:17 2012
> New Revision: 167718
>
> URL: http://llvm.org/viewvc/llvm-project?rev=167718&view=rev
> Log:
> Fix PR14314
>
> - Fix operand order for atomic sub, where the minuend is the value
>   loaded from memory and the subtrahend is the parameter specified.
>
>
> Added:
>     llvm/trunk/test/CodeGen/X86/pr14314.ll
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>     llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=167718&r1=167717&r2=167718&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 12 00:49:17 2012
> @@ -12729,8 +12729,8 @@
>    case X86::ATOMSUB6432: {
>      unsigned HiOpc;
>      unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
> -    BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg).addReg(LoReg);
> -    BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg).addReg(HiReg);
> +    BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
> +    BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
>      break;
>    }
>    case X86::ATOMNAND6432: {
>
> Modified: llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll?rev=167718&r1=167717&r2=167718&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll Mon Nov 12 00:49:17 2012
> @@ -10,10 +10,10 @@
>  ; CHECK: movl ([[REG:%[a-z]+]]), %eax
>  ; CHECK: movl 4([[REG]]), %edx
>  ; CHECK: LBB0_1:
> -; CHECK: movl $1
> -; CHECK: addl
> -; CHECK: movl $0
> -; CHECK: adcl
> +; CHECK: movl %eax, %ebx
> +; CHECK: addl {{%[a-z]+}}, %ebx
> +; CHECK: movl %edx, %ecx
> +; CHECK: adcl {{%[a-z]+}}, %ecx
>  ; CHECK: lock
>  ; CHECK-NEXT: cmpxchg8b ([[REG]])
>  ; CHECK-NEXT: jne
>
> Added: llvm/trunk/test/CodeGen/X86/pr14314.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr14314.ll?rev=167718&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/pr14314.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/pr14314.ll Mon Nov 12 00:49:17 2012
> @@ -0,0 +1,13 @@
> +; RUN: llc < %s -mtriple=i386-pc-linux -mcpu=corei7 | FileCheck %s
> +
> +define i64 @atomicSub(i64* %a, i64 %b) nounwind {
> +entry:
> +  %0 = atomicrmw sub i64* %a, i64 %b seq_cst
> +  ret i64 %0
> +; CHECK: atomicSub
> +; movl %eax, %ebx
> +; subl {{%[a-z]+}}, %ebx
> +; movl %edx, %ecx
> +; sbbl {{%[a-z]+}}, %ecx
> +; CHECK: ret
> +}

It looks like you messed up the CHECK lines here.

-Eli