[llvm-commits] [PATCH] PowerPC: Expand load extend vector operations

[Hal Finkel]

----- Original Message -----
> From: "Adhemerval Zanella" <azanella at linux.vnet.ibm.com>
> To: llvm-commits at cs.uiuc.edu
> Sent: Monday, November 5, 2012 7:22:25 AM
> Subject: [llvm-commits] [PATCH] PowerPC: Expand load extend vector operations
> 
> This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for
> vector types when Altivec is enabled. This patch avoid llvm on PPC
> with
> altivec enbled to fail with expand code like:
> 
> define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
>   %b = trunc <8 x i16> %a to <8 x i8>
>   %c = sext <8 x i8> %b to <8 x i16>
>   ret <8 x i16> %c
> }
> 
> Testcase included and tested on X86_64 and PPC64. Any comments, tips,
> advices?

One quick comment: the FileCheck does a prefix match on the check string, so it is not really necessary to include 'match everything' trailing regex patterns. For example:
+; CHECK: lbz {{[0-9]+}}, {{[-]*[0-9]+}}({{[0-9]+}})
could be just
+; CHECK: lbz

On one hand, the extra patterns serve as an extra check on the asm printer. On the other hand, I think that they might make the tests harder to read. I'll leave it up to you (or, if anyone else has an opinion, please share).

Otherwise, LGTM.

Thanks again,
Hal

> 
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-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory