[llvm-commits] [PATCH][Review Requested] Fix incorrect scheduling of inline assembly referencing memory

[Andrew Trick]

Hi Preston,

Go ahead and commit this. I consider it a necessary workaround until someone else comes up with a less brutal fix...

Still tracking it internally.
<rdar://problem/12033048> [PR13504] INLINEASM doesn't implement mayLoad and mayStore

-Andy

On Oct 26, 2012, at 3:26 PM, "Gurd, Preston" <preston.gurd at intel.com> wrote:

> Here is a patch which fixes the problem with the Post RA scheduler generating an incorrect instruction sequence due to it not being aware that an inline assembly instruction may reference memory. This patch fixes the problem by causing the scheduler to always assume that any inline assembly code instruction could touch memory. This is necessary because the internal representation of the inline instruction does not include any information about memory accesses.
>  
> This should fix PR13504.
>  
> The patch also includes a test case.
>  
> Please review!
>  
> --
> Preston Gurd <preston.gurd at intel.com>
>   Intel Waterloo
>   SSG/DPD/ECDL/DMP
>  
> <sched-bug.patch>

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