[llvm-commits] [llvm] r166747 - /llvm/trunk/test/CodeGen/Mips/setgek.ll

[David Blaikie]

On Thu, Oct 25, 2012 at 11:09 PM, Reed Kotler <rkotler at mips.com> wrote:
> I thought it was safe to match two registers but it seems that sometimes the
> compiler is flipping the operands to XOR  so it could mismatch and then fail
> the make check. It happened to me on one of my internal working branches so
> I changed it back to more general register matching.
>
> I try and make the tests as good as possible as far as matching, but not
> doing things that could change and make the test fail (unless there was a
> real regression).

OK, if I understand you correctly it sounds like you made the change
so the test isn't overconstrained & it won't fail when you make
unrelated changes. But when the compiler isn't changed, the test
output doesn't change - just that unrelated changes might make minor
tweaks to the test output that aren't relevant?

That's totally OK - thanks for the explanation.

>
> On 10/25/2012 10:50 PM, David Blaikie wrote:
>>
>> On Thu, Oct 25, 2012 at 6:29 PM, Reed Kotler <rkotler at mips.com> wrote:
>>>
>>> Author: rkotler
>>> Date: Thu Oct 25 20:29:42 2012
>>> New Revision: 166747
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=166747&view=rev
>>> Log:
>>> fix test setgek.ll so that it will not give false "make check"
>>> failure in some cases
>>
>> What exactly do you mean by some cases? Compiler output should be
>> entirely stable. What about this test is varying?
>>
>>> Modified:
>>>      llvm/trunk/test/CodeGen/Mips/setgek.ll
>>>
>>> Modified: llvm/trunk/test/CodeGen/Mips/setgek.ll
>>> URL:
>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setgek.ll?rev=166747&r1=166746&r2=166747&view=diff
>>>
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/Mips/setgek.ll (original)
>>> +++ llvm/trunk/test/CodeGen/Mips/setgek.ll Thu Oct 25 20:29:42 2012
>>> @@ -12,7 +12,7 @@
>>>     %conv = zext i1 %cmp to i32
>>>     store i32 %conv, i32* @r1, align 4
>>>   ; 16:  slti    ${{[0-9]+}}, -32768
>>> -; 16:  move    $[[REGISTER:[0-9]+]], $t8
>>> -; 16:  xor     ${{[0-9]+}}, $[[REGISTER]]
>>> +; 16:  move    ${{[0-9]+}}, $t8
>>> +; 16:  xor     ${{[0-9]+}}, ${{[0-9]+}}
>>>     ret void
>>>   }
>>>
>>>
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>
>