[llvm-commits] [PATCH] PowerPC: More support for Altivec compare operations

[Will Schmidt]

On Wed, 2012-10-24 at 12:49 -0200, Adhemerval Zanella wrote:
> My previous patch for altivec compare support was incomplete, it
> didn't handle
> the other operators (!=, <, >, etc.). This patch add a better and more
> complete
> support for comparisons for altivec supported types (v16i8, v8i16,
> v4i32, and
> v4f32).
> 
> The testcase also covers all the supported comparison operators for
> the altivec
> types.
> 
> Any tips, suggestions, comments?
> 
> 
> 
> 
> 
> 
> 
> 
> differences
> between files
> attachment
> (0001-PowerPC-More-support-for-Altivec-compare-operations.patch)
> 
> From d129514d6fcde602109dcb27f108ca5642988685 Mon Sep 17 00:00:00 2001
> From: Adhemerval Zanella <azanella at linux.vnet.ibm.com>
> Date: Wed, 24 Oct 2012 12:43:56 -0200
> Subject: [PATCH] PowerPC: More support for Altivec compare operations
> 
> This patch adds more support for vector type comparisons using
> altivec.
> It adds correct support for v16i8, v8i16, v4i32, and v4f32 vector
> types
> for comparison operators ==, !=, >, >=, <, and <=.
> ---
>  lib/Target/PowerPC/PPCISelDAGToDAG.cpp |  174 +++++++++++-
>  lib/Target/PowerPC/PPCInstrAltivec.td  |    2 +-
>  test/CodeGen/PowerPC/vec_cmp.ll        |  470
> +++++++++++++++++++++++++++++++-
>  3 files changed, 617 insertions(+), 29 deletions(-)
> 
> diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> index 6195441..c3e89f0 100644
> --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> @@ -623,6 +623,104 @@ static unsigned getCRIdxForSetCC(ISD::CondCode
> CC, bool &Invert, int &Other) {
>    }
>  }
> 
> +// getVSPLATInst: return the vector splat instruction based on the
> specified
> +// vector type. Since this is for altivec specific code, only support
> the
> +// altivec types (v16i8, v8i16, v4i32, and v4f32).
> +static unsigned int getVSPLATInst(MVT::SimpleValueType VecVT) {
> +  switch (VecVT) {
> +    case MVT::v16i8: return PPC::VSPLTISB;
> +    case MVT::v8i16: return PPC::VSPLTISH;
> +    case MVT::v4i32: return PPC::VSPLTISW;
> +    case MVT::v4f32: return PPC::VSPLTISW;
> +    default:
> +      llvm_unreachable("Invalid vector type");
> +  }
> +}
> +
> +// getVCMPInst: return the vector compare instruction for the
> specified
> +// vector type and condition code. Since this is for altivec specific
> code,
> +// only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
> +static unsigned int getVCMPInst(MVT::SimpleValueType VecVT,
> ISD::CondCode CC) {
> +  switch (CC) {
> +    case ISD::SETEQ:
> +    case ISD::SETUEQ:
> +    case ISD::SETNE:
> +    case ISD::SETUNE:
> +      switch (VecVT) {
> +        case MVT::v16i8: return PPC::VCMPEQUB;
> +        case MVT::v8i16: return PPC::VCMPEQUH;
> +        case MVT::v4i32: return PPC::VCMPEQUW;
> +        // v4f32 != v4f32 could be translate to unordered not equal
> +        case MVT::v4f32: return PPC::VCMPEQFP;
> +        default:
> +          llvm_unreachable("Invalid vector type with conditional
> code");

I see six "Invalid vector type with conditional code" string within
getVCMPInst().   Can these be updated to indicate which case we are in?
i.e. "Invalid vector type with conditional code (ISD::SETUNE) " 



> +      }
> +    case ISD::SETLT:
> +    case ISD::SETGT:
> +    case ISD::SETLE:
> +    case ISD::SETGE:
> +      switch (VecVT) {
> +        case MVT::v16i8: return PPC::VCMPGTSB;
> +        case MVT::v8i16: return PPC::VCMPGTSH;
> +        case MVT::v4i32: return PPC::VCMPGTSW;
> +        default:
> +          llvm_unreachable("Invalid vector type with conditional
> code");
> +      }

<snip>




> diff --git a/test/CodeGen/PowerPC/vec_cmp.ll
> b/test/CodeGen/PowerPC/vec_cmp.ll
> index b2b59db..3aba15a 100644
> --- a/test/CodeGen/PowerPC/vec_cmp.ll
> +++ b/test/CodeGen/PowerPC/vec_cmp.ll
> @@ -1,6 +1,9 @@
> -; RUN: llc -mattr=+altivec < %s | FileCheck %s
> +; RUN: llc -mattr=+altivec -mcpu=pwr6 < %s | FileCheck %s
> 
> -; Check vector comparisons using altivec.
> +; Check vector comparisons using altivec. For non native types, just
> basic
> +; comparison instruction check is done. For altivec supported type
> (16i8,
> +; 8i16, 4i32, and 4f32) all the comparisons operators (==, !=, >, >=,
> <, <=)
> +; are checked.
> 
> 
>  target datalayout =
> "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
> @@ -33,13 +36,134 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8>
> %y) nounwind readnone {
>  ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
> 
> 
> -define <16 x i8> @v16si8_cmp(<16 x i8> %x, <16 x i8> %y) nounwind
> readnone {
> +; Adicional tests for v16i8 since it is a altivec native type
> +

Additional   (several additional instances later in the patch)

Thanks, 
-Will