[llvm-commits] [llvm] r165506 - in /llvm/trunk/lib/Target/Mips: AsmParser/MipsAsmParser.cpp Mips64InstrInfo.td
Jim Grosbach
grosbach at apple.com
Wed Oct 10 13:26:50 PDT 2012
<llvm-source-dir>/test/MC/Mips
Theoretically, there should be near exhaustive tests for the instruction encodings and the assembler parsing there that gets built up as the assembler support gets added to the target. If that's not been the case so far, I strongly recommend that those involved in the assembler fix that. Those tests are extremely valuable whenever instruction patterns get refactored.
-Jim
On Oct 10, 2012, at 1:21 PM, David Chisnall <csdavec at swan.ac.uk> wrote:
> Where are MIPS assembly test cases supposed to go? None of the previous commits that I checked were accompanied by test cases.
>
> David
>
> On 10 Oct 2012, at 20:45, Rafael Espíndola wrote:
>
>> testcase?
>>
>> On 9 October 2012 12:27, David Chisnall <csdavec at swan.ac.uk> wrote:
>>> Author: theraven
>>> Date: Tue Oct 9 11:27:43 2012
>>> New Revision: 165506
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=165506&view=rev
>>> Log:
>>> Improvements to MIPS64 assembler:
>>>
>>> - Teach it about dadd[i] instructions and move pseudo-instruction
>>> - Make it parse the register names correctly (for N32 / N64)
>>>
>>>
>>> Modified:
>>> llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
>>> llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=165506&r1=165505&r2=165506&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
>>> +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Oct 9 11:27:43 2012
>>> @@ -415,48 +415,82 @@
>>>
>>> int MipsAsmParser::matchRegisterName(StringRef Name) {
>>>
>>> - int CC = StringSwitch<unsigned>(Name)
>>> - .Case("zero", Mips::ZERO)
>>> - .Case("a0", Mips::A0)
>>> - .Case("a1", Mips::A1)
>>> - .Case("a2", Mips::A2)
>>> - .Case("a3", Mips::A3)
>>> - .Case("v0", Mips::V0)
>>> - .Case("v1", Mips::V1)
>>> - .Case("s0", Mips::S0)
>>> - .Case("s1", Mips::S1)
>>> - .Case("s2", Mips::S2)
>>> - .Case("s3", Mips::S3)
>>> - .Case("s4", Mips::S4)
>>> - .Case("s5", Mips::S5)
>>> - .Case("s6", Mips::S6)
>>> - .Case("s7", Mips::S7)
>>> - .Case("k0", Mips::K0)
>>> - .Case("k1", Mips::K1)
>>> - .Case("sp", Mips::SP)
>>> - .Case("fp", Mips::FP)
>>> - .Case("gp", Mips::GP)
>>> - .Case("ra", Mips::RA)
>>> - .Case("t0", Mips::T0)
>>> - .Case("t1", Mips::T1)
>>> - .Case("t2", Mips::T2)
>>> - .Case("t3", Mips::T3)
>>> - .Case("t4", Mips::T4)
>>> - .Case("t5", Mips::T5)
>>> - .Case("t6", Mips::T6)
>>> - .Case("t7", Mips::T7)
>>> - .Case("t8", Mips::T8)
>>> - .Case("t9", Mips::T9)
>>> - .Case("at", Mips::AT)
>>> - .Case("fcc0", Mips::FCC0)
>>> - .Default(-1);
>>> -
>>> - if (CC != -1) {
>>> - // 64 bit register in Mips are following 32 bit definitions.
>>> - if (isMips64())
>>> - CC++;
>>> + int CC;
>>> + if (!isMips64())
>>> + CC = StringSwitch<unsigned>(Name)
>>> + .Case("zero", Mips::ZERO)
>>> + .Case("a0", Mips::A0)
>>> + .Case("a1", Mips::A1)
>>> + .Case("a2", Mips::A2)
>>> + .Case("a3", Mips::A3)
>>> + .Case("v0", Mips::V0)
>>> + .Case("v1", Mips::V1)
>>> + .Case("s0", Mips::S0)
>>> + .Case("s1", Mips::S1)
>>> + .Case("s2", Mips::S2)
>>> + .Case("s3", Mips::S3)
>>> + .Case("s4", Mips::S4)
>>> + .Case("s5", Mips::S5)
>>> + .Case("s6", Mips::S6)
>>> + .Case("s7", Mips::S7)
>>> + .Case("k0", Mips::K0)
>>> + .Case("k1", Mips::K1)
>>> + .Case("sp", Mips::SP)
>>> + .Case("fp", Mips::FP)
>>> + .Case("gp", Mips::GP)
>>> + .Case("ra", Mips::RA)
>>> + .Case("t0", Mips::T0)
>>> + .Case("t1", Mips::T1)
>>> + .Case("t2", Mips::T2)
>>> + .Case("t3", Mips::T3)
>>> + .Case("t4", Mips::T4)
>>> + .Case("t5", Mips::T5)
>>> + .Case("t6", Mips::T6)
>>> + .Case("t7", Mips::T7)
>>> + .Case("t8", Mips::T8)
>>> + .Case("t9", Mips::T9)
>>> + .Case("at", Mips::AT)
>>> + .Case("fcc0", Mips::FCC0)
>>> + .Default(-1);
>>> + else
>>> + CC = StringSwitch<unsigned>(Name)
>>> + .Case("zero", Mips::ZERO_64)
>>> + .Case("at", Mips::AT_64)
>>> + .Case("v0", Mips::V0_64)
>>> + .Case("v1", Mips::V1_64)
>>> + .Case("a0", Mips::A0_64)
>>> + .Case("a1", Mips::A1_64)
>>> + .Case("a2", Mips::A2_64)
>>> + .Case("a3", Mips::A3_64)
>>> + .Case("a4", Mips::T0_64)
>>> + .Case("a5", Mips::T1_64)
>>> + .Case("a6", Mips::T2_64)
>>> + .Case("a7", Mips::T3_64)
>>> + .Case("t4", Mips::T4_64)
>>> + .Case("t5", Mips::T5_64)
>>> + .Case("t6", Mips::T6_64)
>>> + .Case("t7", Mips::T7_64)
>>> + .Case("s0", Mips::S0_64)
>>> + .Case("s1", Mips::S1_64)
>>> + .Case("s2", Mips::S2_64)
>>> + .Case("s3", Mips::S3_64)
>>> + .Case("s4", Mips::S4_64)
>>> + .Case("s5", Mips::S5_64)
>>> + .Case("s6", Mips::S6_64)
>>> + .Case("s7", Mips::S7_64)
>>> + .Case("t8", Mips::T8_64)
>>> + .Case("t9", Mips::T9_64)
>>> + .Case("kt0", Mips::K0_64)
>>> + .Case("kt1", Mips::K1_64)
>>> + .Case("gp", Mips::GP_64)
>>> + .Case("sp", Mips::SP_64)
>>> + .Case("fp", Mips::FP_64)
>>> + .Case("s8", Mips::FP_64)
>>> + .Case("ra", Mips::RA_64)
>>> + .Default(-1);
>>> +
>>> + if (CC != -1)
>>> return CC;
>>> - }
>>>
>>> if (Name[0] == 'f') {
>>> StringRef NumString = Name.substr(1);
>>> @@ -544,7 +578,8 @@
>>> if (RegNum > 31)
>>> return -1;
>>>
>>> - return getReg(Mips::CPURegsRegClassID, RegNum);
>>> + // MIPS64 registers are numbered 1 after the 32-bit equivalents
>>> + return getReg(Mips::CPURegsRegClassID, RegNum) + isMips64();
>>> }
>>>
>>> int MipsAsmParser::tryParseRegister(StringRef Mnemonic) {
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=165506&r1=165505&r2=165506&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
>>> +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Oct 9 11:27:43 2012
>>> @@ -83,6 +83,8 @@
>>> //===----------------------------------------------------------------------===//
>>> let DecoderNamespace = "Mips64" in {
>>> /// Arithmetic Instructions (ALU Immediate)
>>> +def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16,
>>> + CPU64Regs>;
>>> def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
>>> CPU64Regs>;
>>> def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
>>> @@ -93,6 +95,7 @@
>>> def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
>>>
>>> /// Arithmetic Instructions (3-Operand, R-Type)
>>> +def DADD : ArithOverflowR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>;
>>> def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
>>> def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
>>> def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
>>> @@ -307,3 +310,8 @@
>>>
>>> // bswap MipsPattern
>>> def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
>>> +
>>> +//===----------------------------------------------------------------------===//
>>> +// Instruction aliases
>>> +//===----------------------------------------------------------------------===//
>>> +def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
>>>
>>>
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