[llvm-commits] [llvm] r165564 - in /llvm/trunk: include/llvm/CodeGen/TargetSchedule.h lib/CodeGen/TargetSchedule.cpp

[Andrew Trick]

Author: atrick
Date: Tue Oct  9 18:44:26 2012
New Revision: 165564

URL: http://llvm.org/viewvc/llvm-project?rev=165564&view=rev
Log:
misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.

Modified:
    llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
    llvm/trunk/lib/CodeGen/TargetSchedule.cpp

Modified: llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetSchedule.h?rev=165564&r1=165563&r2=165564&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetSchedule.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetSchedule.h Tue Oct  9 18:44:26 2012
@@ -45,11 +45,11 @@
   /// Return true if this machine model includes an instruction-level scheduling
   /// model. This is more detailed than the course grain IssueWidth and default
   /// latency properties, but separate from the per-cycle itinerary data.
-  bool hasInstrSchedModel() const { return SchedModel.hasInstrSchedModel(); }
+  bool hasInstrSchedModel() const;
 
   /// Return true if this machine model includes cycle-to-cycle itinerary
   /// data. This models scheduling at each stage in the processor pipeline.
-  bool hasInstrItineraries() const { return !InstrItins.isEmpty(); }
+  bool hasInstrItineraries() const;
 
   /// computeOperandLatency - Compute and return the latency of the given data
   /// dependent def and use when the operand indices are already known. UseMI

Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=165564&r1=165563&r2=165564&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Tue Oct  9 18:44:26 2012
@@ -27,6 +27,14 @@
 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
   cl::desc("Use InstrItineraryData for latency lookup"));
 
+bool TargetSchedModel::hasInstrSchedModel() const {
+  return EnableSchedModel && SchedModel.hasInstrSchedModel();
+}
+
+bool TargetSchedModel::hasInstrItineraries() const {
+  return EnableSchedItins && !InstrItins.isEmpty();
+}
+
 void TargetSchedModel::init(const MCSchedModel &sm,
                             const TargetSubtargetInfo *sti,
                             const TargetInstrInfo *tii) {
@@ -47,14 +55,12 @@
   if (FindMin) {
     // If MinLatency is invalid, then use the itinerary for MinLatency. If no
     // itinerary exists either, then use single cycle latency.
-    if (SchedModel.MinLatency < 0
-        && !(EnableSchedItins && hasInstrItineraries())) {
+    if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
       return 1;
     }
     return SchedModel.MinLatency;
   }
-  else if (!(EnableSchedModel && hasInstrSchedModel())
-           && !(EnableSchedItins && hasInstrItineraries())) {
+  else if (!hasInstrSchedModel() && !hasInstrItineraries()) {
     return TII->defaultDefLatency(&SchedModel, DefMI);
   }
   // ...operand lookup required
@@ -123,7 +129,7 @@
   if (DefLatency >= 0)
     return DefLatency;
 
-  if (EnableSchedItins && hasInstrItineraries()) {
+  if (hasInstrItineraries()) {
     int OperLatency = 0;
     if (UseMI) {
       OperLatency =
@@ -145,7 +151,7 @@
                               TII->defaultDefLatency(&SchedModel, DefMI));
     return InstrLatency;
   }
-  assert(!FindMin && EnableSchedModel && hasInstrSchedModel() &&
+  assert(!FindMin && hasInstrSchedModel() &&
          "Expected a SchedModel for this cpu");
   const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
   unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);