[llvm-commits] [PATCH] Fix instruction selection for vduplane from v4f32 to v2f32

[Silviu Baranga]

Hi David,

 

The main problem is that the code written so far (before r163304) is
assuming

that type of the input value for vduplane is the same as the output type.
This is natural,

since it reflects the actual vdup instruction.

 

The pattern solution is identical to what I suggest, only it is in a
different place.

There could be problems that we don't know about between the build_vector
lowering

code and the instruction selection phase.

 

Cheers,

Silviu

 

From: David Peixotto [mailto:dpeixott at codeaurora.org] 
Sent: 27 September 2012 17:41
To: Silviu Baranga; James Molloy; llvm-commits at cs.uiuc.edu
Subject: RE: [llvm-commits] [PATCH] Fix instruction selection for vduplane
from v4f32 to v2f32

 

Hi Silviu,

 

Thanks for the suggestion. That sounds like another way to fix the issue. We
started seeing failures after r163304 that added extra support for vduplane
(http://llvm.org/viewvc/llvm-project?view=rev
<http://llvm.org/viewvc/llvm-project?view=rev&revision=163304>
&revision=163304). That change was a nice feature and I thought it had just
missed a few patterns for going from Q to D vectors.

 

Is there a disadvantage to adding these patterns? If I understand correctly,
I think the patterns are essentially doing what you suggest, but doing it in
the instruction selector itself rather than with code.

 

-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
by The Linux Foundation

 

 

From: Silviu Baranga [mailto:silbar01 at arm.com] 
Sent: Thursday, September 27, 2012 2:02 AM
To: 'David Peixotto'; James Molloy; llvm-commits at cs.uiuc.edu
Subject: RE: [llvm-commits] [PATCH] Fix instruction selection for vduplane
from v4f32 to v2f32

 

Hi David,

 

Wouldn't it be better to fix the original problem? 

 

It seems that the problem is that the BUILD_VECTOR lowering code is creating
a VDUPLANE 

node that takes a v4i32/v4f32 and creates a v2i32/v2f32. It shouldn't do
that. It should extract

the D subreg and do a VDUPLANE on that in this case.

 

Cheers,

Silviu

From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of David Peixotto
Sent: 27 September 2012 00:55
To: llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] [PATCH] Fix instruction selection for vduplane from
v4f32 to v2f32

 

We are seeing some instruction selection failures for vduplane from larger
vectors to smaller vectors. See PR13938:
http://llvm.org/bugs/show_bug.cgi?id=13938.

 

A patch to fix this issue is attached.

 

This patch fixes an instruction selection failure for

ARMISD::VDUPLANE. The selector was missing patterns for using vdup

to initialize a vector when the source vector is a Q-reg and the

destination vector is a D-reg. The fix is to add new patterns to

allow the selector to properly select this pattern.

 

-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
by The Linux Foundation

 

 
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