[llvm-commits] [PATCH] Use vld1/vst1 for unaligned load/store

[Stepan Dyatkovskiy]

After 15 hours of non-stop programming, I mixed up VLD1 with 
LDRB_POST_IMM since these instructions are used together in some cases. 
Sorry :-)

Of course it is not needed:
> +        const TargetRegisterClass *TRCnopc =
> +            (const TargetRegisterClass*)&ARM::GPRnopcRegClass;

> 2. What is ldrOpc is not a VLD1 opcode?
As I said, VLD1 is OK. SDNode for LDRB_POST_IMM is invalid: number of 
registers added to SDNode fewer that described in .td.

7 ops is needed, but SDNode with only 6 is created. For fast comparison, 
you can look in generated code ARMGenInstrInfo.inc. At LDRB_POST_IMM 
description and its OperandInfo52.

In more details:
In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, 
offset operand is defined as am2offset_imm. am2offset_imm is complex 
parameter type, and actually it consists from dummy register and imm 
itself. As I understood trick with dummy reg was made for AsmParser. In 
ARMISelLowering.cpp, this dummy register was not added to SDNode, and it 
cause crash in Peephole Optimizer pass.

The code for Thumb2 mode (t2LDRB_POST) seems to be correct.

Fixed patch is reattached.

P.S.: perhaps move that to another thread?

-Stepan.


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