[llvm-commits] [patch] Enable the generation of vaddl-type instructions from extloads on ARM

[Jim Grosbach]

Hi Silviu,

Thanks for the update. This is definitely much better. Why do we need any ARM specific code here, though? Given the problem description, it seems like this is something the legalizer should be able to reason about without needing custom handling in the target.

-Jim


On Sep 6, 2012, at 9:34 AM, Silviu Baranga <silbar01 at arm.com> wrote:

> Hi Jim,
> 
> Thanks for the review. The BREAK node solution was a bit ugly.
> 
> I've attached a new patch that solves this without a BREAK node.
> This is done by stopping the folding of nodes zext nodes when
> this will result in a non-legal operation.
> 
> I also had to stop the (zext (zextload x)) folding for vector
> types. This is already being done for sext nodes.
> 
> Thanks,
> Silviu
> 
>> -----Original Message-----
>> From: Jim Grosbach [mailto:grosbach at apple.com]
>> Sent: 06 September 2012 01:42
>> To: Silviu Baranga
>> Cc: llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [patch] Enable the generation of vaddl-type
>> instructions from extloads on ARM
>> 
>> Hi Silviu,
>> 
>> I like the idea of teaching the compiler to use these instructions, but
>> the BREAK pseudo-instruction feels pretty gross to me. I'd much prefer
>> we figure out how to teach the combiner and isel to be smarter directly
>> rather than doing something like that.
>> 
>> -Jim
>> 
>> On Sep 4, 2012, at 1:58 AM, Silviu Baranga <silbar01 at arm.com> wrote:
>> 
>>> Hi,
>>> 
>>> Currently LLVM will not generate a vaddl-type instructions when an
>> extload
>>> node is in the input dag. All vector extload nodes are implemented
>> with
>>> a load instruction and a lengthening instruction on ARM. If the
>> lengthening
>>> instruction is followed by an add instruction, it would be better to
>>> generate
>>> a vaddl-type instruction instead.
>>> 
>>> To do this, we split all lengthening dag nodes which extend a type to
>> more
>>> then twice its size (this is OK because these nodes would be
>> implemented by
>>> multiple instructions anyway) into two lengthening nodes. One node
>> will be
>>> later
>>> combined to form the extload node, and the other can be selected as
>> part of
>>> a
>>> vaddl-type instruction (there are already patterns for this).
>>> 
>>> To stop the dag nodes from re-combining, we insert a BREAK node
>> between
>>> them. The
>>> BREAK node is used as an optimization barrier for the DAG combiner,
>> and
>>> might be
>>> useful in other cases as well. We remove the BREAK node in the
>> instruction
>>> selection stage.
>>> 
>>> This approach allows the reuse of existing selection patterns.
>>> 
>>> This patch depends on the following other patch:
>>> http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-
>> 20120827/149201.
>>> html
>>> 
>>> Please review!
>>> 
>>> Thanks,
>>> Silviu<patch.diff>_______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 
> <zext_split.diff>