[llvm-commits] [PATCH] DAG post-process for Hexagon MI scheduler

Andrew Trick atrick at apple.com
Thu Sep 13 15:44:52 PDT 2012 

On Sep 13, 2012, at 3:29 PM, Sergei Larin <slarin at codeaurora.org> wrote:

> Hello Andy, Hello everyone,
> 
>  This patch introduces a possibility for Hexagon MI scheduler to perform
> some target specific post- processing on the scheduling DAG prior to
> scheduling.
> 
>  - Currently it only enforces one kind of scheduling hazard, but could be
> extended in the future
>  - it only modifies Hexagon back end
>  - it passes make check-all
> 
>  As a general idea - this is a fast and simple way to enforce some
> scheduling rules that are awkward to enforce in any other way - like one
> kind of instruction not to bypass another one while there are no
> dependencies or hw hazards between them. It is conceptually different from
> DFA and not easily doable with HazardRecognizer. If the idea is applicable
> to any other back end, maybe a common interface to MachineSchedStrategy
> would be practical.

LGTM. Go ahead and checkin.

I like the idea of initializing MachineSchedStrategy only after the DAG is ready to be scheduled. So this is a good example of when you should subclass and extend ScheduleDAGMI (before now you really didn't need to do that). Since post-processing the DAG is such an obvious thing for a Target to do, I'll add a virtual call in ScheduleDAGMI so it can be done without overriding the driver.

-Andy

> ---
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
> The Linux Foundation
> 
> 
>> -----Original Message-----
>> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
>> bounces at cs.uiuc.edu] On Behalf Of Sergei Larin
>> Sent: Tuesday, September 11, 2012 12:05 PM
>> To: 'Andrew Trick'
>> Cc: llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [PATCH] Heuristic changes to Hexagon MI
>> scheduler
>> 
>> Andy,
>> 
>>> NumPreds/SuccsLeft are public members of SUnit. So I don't think you
>>> need getSingleUnscheduledPred/Succ helpers. In this case you already
>>> know that the Pred/Succ is unscheduled, so you can just check the
>>> count.
>> 
>> The problem here seems to be due to aliasing edges in DAG. We could
>> have nodes that look like this:
>> 
>> SU(54):   ADJCALLSTACKDOWN 0, %R29<imp-def>, %R30<imp-def>, %R31<imp-
>> use>,
>> %R30<imp-use>, %R29<imp-use>
>>  # preds left       : 5
>>  # succs left       : 0
>>  # rdefs left       : 0
>>  Latency            : 1
>>  Depth              : 20
>>  Height             : 1
>>  Predecessors:
>>   out SU(53): Latency=1
>>   val SU(53): Latency=1 Reg=%R29
>>   out SU(53): Latency=1
>>   val SU(53): Latency=1 Reg=%R30
>>   val SU(53): Latency=1 Reg=%R31
>>  Successors:
>>   out SU(57): Latency=1
>>   val SU(57): Latency=1
>>   out SU(57): Latency=1
>>   antiSU(56): Latency=0
>> 
>> SU(53):   ADJCALLSTACKUP 0, 0, %R29<imp-def>, %R30<imp-def>, %R31<imp-
>> def>,
>> %R29<imp-use>
>>  # preds left       : 4
>>  # succs left       : 5
>>  # rdefs left       : 0
>>  Latency            : 1
>>  Depth              : 19
>>  Height             : 2
>>  Predecessors:
>>   out SU(52): Latency=1
>>   out SU(49): Latency=1
>>   val SU(49): Latency=1 Reg=%R29
>>   out SU(49): Latency=1
>>  Successors:
>>   out SU(54): Latency=1
>>   val SU(54): Latency=1
>>   out SU(54): Latency=1
>>   val SU(54): Latency=1
>>   out SU(56): Latency=1
>>   val SU(54): Latency=1
>> 
>> Going bottom-up, considering SU(54). SU(56) is already scheduled. It
>> has one predecessor which is 53, but it is listed 5 times... So for 53
>> #succs left == 5
>> 
>> The helper function is somewhat expensive, but gets it right.
>> Simplified check would need to make sure no aliasing is involved, and
>> will require same number of iterations. It also looks like no other
>> case is affected by this at the moment, but someone unaware of this
>> possibility can easily get confused in the future.
>> 
>> So I'll keep the helper function for now, until we find a better way
>> to treat aliasing edges.
>> 
>> Thanks.
>> 
>> Sergei
>> 
>> ---
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> hosted by The Linux Foundation
>> 
>> 
>>> -----Original Message-----
>>> From: Andrew Trick [mailto:atrick at apple.com]
>>> Sent: Thursday, September 06, 2012 7:43 PM
>>> To: Sergei Larin
>>> Cc: llvm-commits at cs.uiuc.edu
>>> Subject: Re: [llvm-commits] [PATCH] Heuristic changes to Hexagon MI
>>> scheduler
>>> 
>>> Hi Sergei,
>>> 
>>> NumPreds/SuccsLeft are public members of SUnit. So I don't think you
>>> need getSingleUnscheduledPred/Succ helpers. In this case you already
>>> know that the Pred/Succ is unscheduled, so you can just check the
>>> count.
>>> 
>>> Other than that, please check it in. As soon as you do, I'll
>>> reorganize MachineScheduler.h to remove a lot of the redundancy.
>>> After my reorg, MachineSchedStrategy and ScheduleDAGMI will become
>>> public, but ConvergingScheduler will still be local. It will look
>> like
>>> you still have redundant code in the register pressure heuristics,
>> but
>>> that's actually what I want. I'll be changing those frequently in the
>>> near future and don't want to affect your target during the churn. I
>>> expect you to end up rewriting those heuristics eventually anyway to
>>> work better for VLIWish targets.
>>> 
>>> -Andy
>>> 
>>> On Sep 5, 2012, at 7:45 AM, Sergei Larin <slarin at codeaurora.org>
>> wrote:
>>> 
>>>> Please review attached patch. It attempts to:
>>>> 
>>>> - Add "blocked" heuristic to the Hexagon MI scheduler
>>>> - Tweak the Hexagon local class hierarchy a bit
>>>> - Clean-up couple minor stylistic violations
>>>> 
>>>> It passes make check-all without any additional issues.
>>>> 
>>>> Thanks.
>>>> 
>>>> Sergei Larin
>>>> 
>>>> ---
>>>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>>>> hosted by The Linux Foundation
>>>> 
>>>> 
>>> 
>> <add_blocked_heuristic_to_Hexagon_MI_scheduler.patch>_________________
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>> 
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