[llvm-commits] [llvm] r163010 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsMCInstLower.cpp lib/Target/Mips/MipsMCInstLower.h test/MC/Mips/mips64extins.ll
Jack Carter
jcarter at mips.com
Fri Aug 31 11:06:48 PDT 2012
Author: jacksprat
Date: Fri Aug 31 13:06:48 2012
New Revision: 163010
URL: http://llvm.org/viewvc/llvm-project?rev=163010&view=rev
Log:
The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
llvm/trunk/test/MC/Mips/mips64extins.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=163010&r1=163009&r2=163010&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Fri Aug 31 13:06:48 2012
@@ -222,6 +222,10 @@
def DEXTM : ExtBase<1, "dextm", CPU64Regs>;
}
def DINS : InsBase<7, "dins", CPU64Regs>;
+let Pattern = []<dag> in {
+ def DINSU : InsBase<6, "dinsu", CPU64Regs>;
+ def DINSM : InsBase<5, "dinsm", CPU64Regs>;
+}
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=163010&r1=163009&r2=163010&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Fri Aug 31 13:06:48 2012
@@ -86,11 +86,11 @@
break;
// Double extract instruction is chosen by pos and size operands
case Mips::DEXT:
- assert(Subtarget->hasMips64() &&
- "DEXT is a MIPS64 instruction");
+ case Mips::DINS:
+ assert(Subtarget->hasMips64() && "DEXT/DINS are MIPS64 instructions");
{
MCInst TmpInst0;
- MCInstLowering.LowerDEXT(I, TmpInst0);
+ MCInstLowering.LowerDextDins(I, TmpInst0);
OutStreamer.EmitInstruction(TmpInst0);
return;
}
Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=163010&r1=163009&r2=163010&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Fri Aug 31 13:06:48 2012
@@ -11,7 +11,6 @@
// MCInst records.
//
//===----------------------------------------------------------------------===//
-
#include "MipsMCInstLower.h"
#include "MipsAsmPrinter.h"
#include "MipsInstrInfo.h"
@@ -190,10 +189,17 @@
}
}
-// Pick a DEXT instruction variant based on the pos and size operands
-void MipsMCInstLower::LowerDEXT(const MachineInstr *MI, MCInst& Inst) {
+// Pick a DEXT or DINS instruction variant based on the pos and size operands
+void MipsMCInstLower::LowerDextDins(const MachineInstr *MI, MCInst& Inst) {
+ int Opcode = MI->getOpcode();
+
+ if (Opcode == Mips::DEXT)
+ assert(MI->getNumOperands() == 4 &&
+ "Invalid no. of machine operands for DEXT!");
+ else // Only DEXT and DINS are possible
+ assert(MI->getNumOperands() == 5 &&
+ "Invalid no. of machine operands for DINS!");
- assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands for DEXT!");
assert(MI->getOperand(2).isImm());
int64_t pos = MI->getOperand(2).getImm();
assert(MI->getOperand(3).isImm());
@@ -204,23 +210,21 @@
// rs
Inst.addOperand(LowerOperand(MI->getOperand(1)));
- // DEXT
- if ((pos < 32) && (size <= 32)) {
- Inst.addOperand(MCOperand::CreateImm(pos));
- Inst.addOperand(MCOperand::CreateImm(size));
- Inst.setOpcode(Mips::DEXT);
- }
- // DEXTU
- else if ((pos < 64) && (size <= 32)) {
- Inst.addOperand(MCOperand::CreateImm(pos - 32));
- Inst.addOperand(MCOperand::CreateImm(size));
- Inst.setOpcode(Mips::DEXTU);
- }
- // DEXTM
- else {
+ if (size <= 32) {
+ if ((pos < 32)) { // DEXT/DINS
+ Inst.addOperand(MCOperand::CreateImm(pos));
+ Inst.addOperand(MCOperand::CreateImm(size));
+ Inst.setOpcode(Opcode);
+ } else { // DEXTU/DINSU
+ Inst.addOperand(MCOperand::CreateImm(pos - 32));
+ Inst.addOperand(MCOperand::CreateImm(size));
+ Inst.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
+ }
+ } else { // DEXTM/DINSM
+ assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
Inst.addOperand(MCOperand::CreateImm(pos));
Inst.addOperand(MCOperand::CreateImm(size - 32));
Inst.setOpcode(Mips::DEXTM);
+ Inst.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
}
- return;
}
Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=163010&r1=163009&r2=163010&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Fri Aug 31 13:06:48 2012
@@ -34,7 +34,7 @@
void Initialize(Mangler *mang, MCContext *C);
void Lower(const MachineInstr *MI, MCInst &OutMI) const;
void LowerLargeShift(const MachineInstr *MI, MCInst &Inst, int64_t Shift);
- void LowerDEXT(const MachineInstr *MI, MCInst &Inst);
+ void LowerDextDins(const MachineInstr *MI, MCInst &Inst);
private:
MCOperand LowerSymbolOperand(const MachineOperand &MO,
Modified: llvm/trunk/test/MC/Mips/mips64extins.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64extins.ll?rev=163010&r1=163009&r2=163010&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64extins.ll (original)
+++ llvm/trunk/test/MC/Mips/mips64extins.ll Fri Aug 31 13:06:48 2012
@@ -26,3 +26,32 @@
ret i64 %and
}
+define i64 @dins(i64 %i, i64 %j) nounwind readnone {
+entry:
+; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
+ %shl2 = shl i64 %j, 8
+ %and = and i64 %shl2, 261888
+ %and3 = and i64 %i, -261889
+ %or = or i64 %and3, %and
+ ret i64 %or
+}
+
+define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
+entry:
+; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 1
+ %shl4 = shl i64 %j, 10
+ %and = and i64 %shl4, 8796093021184
+ %and5 = and i64 %i, -8796093021185
+ %or = or i64 %and5, %and
+ ret i64 %or
+}
+
+define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
+entry:
+; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 8, 13
+ %shl4 = shl i64 %j, 40
+ %and = and i64 %shl4, 9006099743113216
+ %and5 = and i64 %i, -9006099743113217
+ %or = or i64 %and5, %and
+ ret i64 %or
+}
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