[llvm-commits] [PATCH] Remove redundant register copies when inserting to Q registers on ARM

[James Molloy]

Hi,

The attached patch improves code generation for NEON when setting one
(<= 32bit) lane of a Q (128 bit) register.

There is no such instruction to implement this natively, because the
vmov.32 instructions work on D registers, not Q registers.

Previously a pattern was used for this, something like

  (INSERT_SUBREG (<set lane> (EXTRACT_SUBREG ... ) ) )

But this caused inefficient code to be generated because when it got to
the machineinstr stage, the live region for the base Q register and the
mutated D subregister overlapped, so they couldn't be coalesced and you
ended up with a pointless copy:

  mov r0, #255
  vorr d19, d21, d21
  vmov.32 d19[1], r0
  vorr d21, d19, d19

This patch adds pseudo instructions that set a lane of a Q register
instead. This is similar to how loads and stores are handled.

Please review!

Cheers,

James

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