[llvm-commits] [llvm] r162878 - /llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Wed Aug 29 18:52:52 2012
New Revision: 162878

URL: http://llvm.org/viewvc/llvm-project?rev=162878&view=rev
Log:
Verify the order of tied operands in inline asm.

When there are multiple tied use-def pairs on an inline asm instruction,
the tied uses must appear in the same order as the defs.

It is possible to write an LLVM IR inline asm instruction that breaks
this constraint, but there is no reason for a front end to emit the
operands out of order.

The gnu inline asm syntax specifies tied operands as a single read/write
constraint "+r", so ouf of order operands are not possible.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=162878&r1=162877&r2=162878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Wed Aug 29 18:52:52 2012
@@ -895,6 +895,7 @@
 
     // Remember to operand index of the group flags.
     SmallVector<unsigned, 8> GroupIdx;
+    unsigned PrevDefGroup = 0;
 
     // Add all of the operand registers to the instruction.
     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
@@ -943,9 +944,20 @@
         if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
           unsigned DefGroup = 0;
           if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
+            // Check that the def groups are monotonically increasing.
+            // Otherwise, the tied uses and defs won't line up, and
+            // MI::findTiedOperandIdx() will find the wrong operand. This
+            // should be automatically enforced by the front ends when
+            // translating "+" constraints into tied def+use pairs.
+            assert(DefGroup >= PrevDefGroup &&
+                   "Tied inline asm operands must be in increasing order.");
+            PrevDefGroup = DefGroup;
+
             unsigned DefIdx = GroupIdx[DefGroup] + 1;
             unsigned UseIdx = GroupIdx.back() + 1;
             for (unsigned j = 0; j != NumVals; ++j) {
+              assert(!MI->getOperand(DefIdx + j).isTied() &&
+                     "Def is already tied to another use");
               MI->getOperand(DefIdx + j).setIsTied();
               MI->getOperand(UseIdx + j).setIsTied();
             }