[llvm-commits] [llvm] r162816 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Tue Aug 28 19:38:03 2012
New Revision: 162816

URL: http://llvm.org/viewvc/llvm-project?rev=162816&view=rev
Log:
Verify the tied operand flags.

WHen running with -verify-machineinstrs, check that tied operands come
in matching use/def pairs, and that they are consistent with MCInstrDesc
when it applies.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=162816&r1=162815&r2=162816&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Aug 28 19:38:03 2012
@@ -703,6 +703,35 @@
         << MI->getNumExplicitOperands() << " given.\n";
   }
 
+  // Check the tied operands.
+  SmallVector<unsigned, 4> TiedDefs;
+  SmallVector<unsigned, 4> TiedUses;
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    const MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg() || !MO.isTied())
+      continue;
+    if (MO.isDef()) {
+      TiedDefs.push_back(i);
+      continue;
+    }
+    TiedUses.push_back(i);
+    if (TiedDefs.size() < TiedUses.size()) {
+      report("No tied def for tied use", &MO, i);
+      break;
+    }
+    if (i >= MCID.getNumOperands())
+      continue;
+    int DefIdx = MCID.getOperandConstraint(i, MCOI::TIED_TO);
+    if (unsigned(DefIdx) != TiedDefs[TiedUses.size() - 1]) {
+      report("Tied def doesn't match MCInstrDesc", &MO, i);
+      *OS << "Descriptor says tied def should be operand " << DefIdx << ".\n";
+    }
+  }
+  if (TiedDefs.size() > TiedUses.size()) {
+    unsigned i = TiedDefs[TiedUses.size() - 1];
+    report("No tied use for tied def", &MI->getOperand(i), i);
+  }
+
   // Check the MachineMemOperands for basic consistency.
   for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
        E = MI->memoperands_end(); I != E; ++I) {
@@ -758,6 +787,14 @@
       if (MO->isImplicit())
         report("Explicit operand marked as implicit", MO, MONum);
     }
+
+    if (MCID.getOperandConstraint(MONum, MCOI::TIED_TO) != -1) {
+      if (!MO->isReg())
+        report("Tied use must be a register", MO, MONum);
+      else if (!MO->isTied())
+        report("Operand should be tied", MO, MONum);
+    } else if (MO->isReg() && MO->isTied())
+      report("Explicit operand should not be tied", MO, MONum);
   } else {
     // ARM adds %reg0 operands to indicate predicates. We'll allow that.
     if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())