[llvm-commits] [PATCH] Execution domain support for VMOV and VLDR

[Jakob Stoklund Olesen]

On Aug 28, 2012, at 5:04 AM, Tim Northover <t.p.northover at gmail.com> wrote:

> On Mon, Aug 20, 2012 at 12:04 PM, Tim Northover <t.p.northover at gmail.com> wrote:
>>> I was thinking - is it possible to somehow make code generic? And not
>>> to do error-prone manual change of instructions...
>> 
>> Hmm. The conversion does feel particularly error-prone. I think the
>> transformations are probably too dissimilar to automate though, even
>> within a single target. We could almost certainly improve things so
>> that a BuildMI is used to make a fresh instruction in all cases.

Hi Tim,

BuildMI() just returns a MachineInstrBuilder, and we already have one of those. I don't think it is worth the added complexity in the ExeDepsFix pass to create new instructions.

If you start by stripping off all the explicit operands:

  for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
     MI->RemoveOperand(i-1);

You can add the new operands just like with a BuildMI:

  MIB.addReg(...).addReg(...)...

It's more important to move these register computations into a function:

      DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_0, &ARM::DPRRegClass);
      Lane = 0;
      if (DReg == ARM::NoRegister) {
        DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_1, &ARM::DPRRegClass);
        Lane = 1;
        assert(DReg && "S-register with no D super-register?");
      }

I thought I saw a patch that did that?

/jakob