[llvm-commits] [llvm] r161769 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/vec_ss_load_fold.ll

[Craig Topper]

I somewhat wonder if folding of scalar intrinsics works completely
correctly. Those intrinsics have VR128 as their register class, but the
load size is actually 32/64-bits. I think the folding code looks at the
register class size to determine size. Adding Jakob for comment.

~Craig

On Mon, Aug 13, 2012 at 11:29 AM, Manman Ren <mren at apple.com> wrote:

> Author: mren
> Date: Mon Aug 13 13:29:41 2012
> New Revision: 161769
>
> URL: http://llvm.org/viewvc/llvm-project?rev=161769&view=rev
> Log:
> X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr
> from
> OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be
> changed
> to a memory operand.
>
> PR13576
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
>     llvm/trunk/test/CodeGen/X86/vec_ss_load_fold.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=161769&r1=161768&r2=161769&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Aug 13 13:29:41 2012
> @@ -414,12 +414,6 @@
>      { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
>      { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
>      { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
> -    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
> -    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
> -    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
> -    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
> -    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
> -    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
>      { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
>      { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
>      { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
> @@ -680,6 +674,12 @@
>      { X86::IMUL64rr,        X86::IMUL64rm,      0 },
>      { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
>      { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
> +    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
> +    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
> +    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
> +    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
> +    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
> +    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
>      { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
>      { X86::MAXPDrr_Int,     X86::MAXPDrm_Int,   TB_ALIGN_16 },
>      { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
>
> Modified: llvm/trunk/test/CodeGen/X86/vec_ss_load_fold.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_ss_load_fold.ll?rev=161769&r1=161768&r2=161769&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vec_ss_load_fold.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vec_ss_load_fold.ll Mon Aug 13 13:29:41
> 2012
> @@ -70,3 +70,17 @@
>  ; CHECK: call
>  ; CHECK: roundss $4, %xmm{{.*}}, %xmm0
>  }
> +
> +; PR13576
> +define  <2 x double> @test5() nounwind uwtable readnone noinline {
> +entry:
> +  %0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double
> +4.569870e+02, double 1.233210e+02>, i32 128) nounwind readnone
> +  ret <2 x double> %0
> +; CHECK: test5:
> +; CHECK: movl
> +; CHECK: mov
> +; CHECK: cvtsi2sd
> +}
> +
> +declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind
> readnone
>
>
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-- 
~Craig
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