[llvm-commits] [llvm] r161628 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMExpandPseudoInsts.cpp ARMJITInfo.cpp ARMLoadStoreOptimizer.cpp AsmParser/ARMAsmParser.cpp MCTargetDesc/ARMBaseInfo.h MCTargetDesc/ARMMCCodeEmitter.cpp
Jim Grosbach
grosbach at apple.com
Thu Aug 9 15:27:23 PDT 2012
Woot! Very cool.
-jim
On Aug 9, 2012, at 3:10 PM, Eric Christopher <echristo at apple.com> wrote:
> Author: echristo
> Date: Thu Aug 9 17:10:21 2012
> New Revision: 161628
>
> URL: http://llvm.org/viewvc/llvm-project?rev=161628&view=rev
> Log:
> Remove getARMRegisterNumbering and replace with calls into
> the register info for getEncodingValue. This builds on the
> small patch of yesterday to set HWEncoding in the register
> file.
>
> One (deprecated) use was turned into a hard number to avoid
> needing register info in the old JIT.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=161628&r1=161627&r2=161628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Aug 9 17:10:21 2012
> @@ -254,7 +254,7 @@
> emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
> return 0;
> }
> - unsigned Reg = getARMRegisterNumbering(MO.getReg());
> + unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
> int32_t Imm12 = MO1.getImm();
> uint32_t Binary;
> Binary = Imm12 & 0xfff;
> @@ -296,7 +296,7 @@
> emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
> return 0;
> }
> - unsigned Reg = getARMRegisterNumbering(MO.getReg());
> + unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
> int32_t Imm12 = MO1.getImm();
>
> // Special value for #-0
> @@ -352,6 +352,12 @@
> void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
> void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
> intptr_t JTBase = 0) const;
> + unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
> + unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
> + unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
> + unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
> + unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
> + unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
> };
> }
>
> @@ -440,7 +446,7 @@
> unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
> const MachineOperand &MO) const {
> if (MO.isReg())
> - return getARMRegisterNumbering(MO.getReg());
> + return II->getRegisterInfo().getEncodingValue(MO.getReg());
> else if (MO.isImm())
> return static_cast<unsigned>(MO.getImm());
> else if (MO.isGlobal())
> @@ -776,7 +782,7 @@
> Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
>
> // Encode Rn which is PC.
> - Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
> + Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift;
>
> // Encode the displacement.
> Binary |= 1 << ARMII::I_BitShift;
> @@ -963,7 +969,7 @@
> if (Rs) {
> // Encode Rs bit[11:8].
> assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
> - return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
> + return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
> }
>
> // Encode shift_imm bit[11:7].
> @@ -1014,7 +1020,7 @@
> Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
> else if (ImplicitRd)
> // Special handling for implicit use (e.g. PC).
> - Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
> + Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
>
> if (MCID.Opcode == ARM::MOVi16) {
> // Get immediate from MI.
> @@ -1064,7 +1070,7 @@
> if (!isUnary) {
> if (ImplicitRn)
> // Special handling for implicit use (e.g. PC).
> - Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
> + Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
> else {
> Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
> ++OpIdx;
> @@ -1081,7 +1087,7 @@
>
> if (MO.isReg()) {
> // Encode register Rm.
> - emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
> + emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg()));
> return;
> }
>
> @@ -1124,14 +1130,14 @@
> // Set first operand
> if (ImplicitRd)
> // Special handling for implicit use (e.g. PC).
> - Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
> + Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
> else
> Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
>
> // Set second operand
> if (ImplicitRn)
> // Special handling for implicit use (e.g. PC).
> - Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
> + Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
> else
> Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
>
> @@ -1158,7 +1164,7 @@
> Binary |= 1 << ARMII::I_BitShift;
> assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
> // Set bit[3:0] to the corresponding Rm register
> - Binary |= getARMRegisterNumbering(MO2.getReg());
> + Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
>
> // If this instr is in scaled register offset/index instruction, set
> // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
> @@ -1202,7 +1208,7 @@
> // Set second operand
> if (ImplicitRn)
> // Special handling for implicit use (e.g. PC).
> - Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
> + Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
> else
> Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
>
> @@ -1221,7 +1227,7 @@
> // If this instr is in register offset/index encoding, set bit[3:0]
> // to the corresponding Rm register.
> if (MO2.getReg()) {
> - Binary |= getARMRegisterNumbering(MO2.getReg());
> + Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
> emitWordLE(Binary);
> return;
> }
> @@ -1287,7 +1293,7 @@
> const MachineOperand &MO = MI.getOperand(i);
> if (!MO.isReg() || MO.isImplicit())
> break;
> - unsigned RegNum = getARMRegisterNumbering(MO.getReg());
> + unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg());
> assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
> RegNum < 16);
> Binary |= 0x1 << RegNum;
> @@ -1530,7 +1536,7 @@
>
> if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
> // The return register is LR.
> - Binary |= getARMRegisterNumbering(ARM::LR);
> + Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR);
> else
> // otherwise, set the return register
> Binary |= getMachineOpValue(MI, 0);
> @@ -1538,11 +1544,12 @@
> emitWordLE(Binary);
> }
>
> -static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
> +unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI,
> + unsigned OpIdx) const {
> unsigned RegD = MI.getOperand(OpIdx).getReg();
> unsigned Binary = 0;
> bool isSPVFP = ARM::SPRRegClass.contains(RegD);
> - RegD = getARMRegisterNumbering(RegD);
> + RegD = II->getRegisterInfo().getEncodingValue(RegD);
> if (!isSPVFP)
> Binary |= RegD << ARMII::RegRdShift;
> else {
> @@ -1552,11 +1559,12 @@
> return Binary;
> }
>
> -static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
> +unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI,
> + unsigned OpIdx) const {
> unsigned RegN = MI.getOperand(OpIdx).getReg();
> unsigned Binary = 0;
> bool isSPVFP = ARM::SPRRegClass.contains(RegN);
> - RegN = getARMRegisterNumbering(RegN);
> + RegN = II->getRegisterInfo().getEncodingValue(RegN);
> if (!isSPVFP)
> Binary |= RegN << ARMII::RegRnShift;
> else {
> @@ -1566,11 +1574,12 @@
> return Binary;
> }
>
> -static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
> +unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI,
> + unsigned OpIdx) const {
> unsigned RegM = MI.getOperand(OpIdx).getReg();
> unsigned Binary = 0;
> bool isSPVFP = ARM::SPRRegClass.contains(RegM);
> - RegM = getARMRegisterNumbering(RegM);
> + RegM = II->getRegisterInfo().getEncodingValue(RegM);
> if (!isSPVFP)
> Binary |= RegM;
> else {
> @@ -1757,28 +1766,31 @@
> emitWordLE(Binary);
> }
>
> -static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
> +unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI,
> + unsigned OpIdx) const {
> unsigned RegD = MI.getOperand(OpIdx).getReg();
> unsigned Binary = 0;
> - RegD = getARMRegisterNumbering(RegD);
> + RegD = II->getRegisterInfo().getEncodingValue(RegD);
> Binary |= (RegD & 0xf) << ARMII::RegRdShift;
> Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
> return Binary;
> }
>
> -static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
> +unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI,
> + unsigned OpIdx) const {
> unsigned RegN = MI.getOperand(OpIdx).getReg();
> unsigned Binary = 0;
> - RegN = getARMRegisterNumbering(RegN);
> + RegN = II->getRegisterInfo().getEncodingValue(RegN);
> Binary |= (RegN & 0xf) << ARMII::RegRnShift;
> Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
> return Binary;
> }
>
> -static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
> +unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI,
> + unsigned OpIdx) const {
> unsigned RegM = MI.getOperand(OpIdx).getReg();
> unsigned Binary = 0;
> - RegM = getARMRegisterNumbering(RegM);
> + RegM = II->getRegisterInfo().getEncodingValue(RegM);
> Binary |= (RegM & 0xf);
> Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
> return Binary;
> @@ -1812,7 +1824,7 @@
> Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
>
> unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
> - RegT = getARMRegisterNumbering(RegT);
> + RegT = II->getRegisterInfo().getEncodingValue(RegT);
> Binary |= (RegT << ARMII::RegRdShift);
> Binary |= encodeNEONRn(MI, RegNOpIdx);
>
> @@ -1841,7 +1853,7 @@
> Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
>
> unsigned RegT = MI.getOperand(1).getReg();
> - RegT = getARMRegisterNumbering(RegT);
> + RegT = II->getRegisterInfo().getEncodingValue(RegT);
> Binary |= (RegT << ARMII::RegRdShift);
> Binary |= encodeNEONRn(MI, 0);
> emitWordLE(Binary);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=161628&r1=161627&r2=161628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Thu Aug 9 17:10:21 2012
> @@ -1009,7 +1009,7 @@
> BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
> unsigned OpIdx = 0;
> unsigned SrcReg = MI.getOperand(1).getReg();
> - unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
> + unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
> unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
> Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
> &ARM::DPR_VFP2RegClass);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp?rev=161628&r1=161627&r2=161628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMJITInfo.cpp Thu Aug 9 17:10:21 2012
> @@ -289,9 +289,9 @@
> if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry)
> ResultPtr = ResultPtr >> 2;
> *((intptr_t*)RelocPos) |= ResultPtr;
> - // Set register Rn to PC.
> - *((intptr_t*)RelocPos) |=
> - getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
> + // Set register Rn to PC (which is register 15 on all architectures).
> + // FIXME: This avoids the need for register info in the JIT class.
> + *((intptr_t*)RelocPos) |= 15 << ARMII::RegRnShift;
> break;
> }
> case ARM::reloc_arm_pic_jt:
>
> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=161628&r1=161627&r2=161628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Thu Aug 9 17:10:21 2012
> @@ -456,8 +456,7 @@
> DebugLoc dl = Loc->getDebugLoc();
> const MachineOperand &PMO = Loc->getOperand(0);
> unsigned PReg = PMO.getReg();
> - unsigned PRegNum = PMO.isUndef() ? UINT_MAX
> - : getARMRegisterNumbering(PReg);
> + unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg);
> unsigned Count = 1;
> unsigned Limit = ~0U;
>
> @@ -483,8 +482,7 @@
> int NewOffset = MemOps[i].Offset;
> const MachineOperand &MO = MemOps[i].MBBI->getOperand(0);
> unsigned Reg = MO.getReg();
> - unsigned RegNum = MO.isUndef() ? UINT_MAX
> - : getARMRegisterNumbering(Reg);
> + unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
> // Register numbers must be in ascending order. For VFP / NEON load and
> // store multiples, the registers must also be consecutive and within the
> // limit on the number of registers per instruction.
>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=161628&r1=161627&r2=161628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Aug 9 17:10:21 2012
> @@ -2908,7 +2908,7 @@
> if (!RC->contains(EndReg))
> return Error(EndLoc, "invalid register in register list");
> // Ranges must go from low to high.
> - if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
> + if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
> return Error(EndLoc, "bad range in register list");
>
> // Add all the registers in the range to the register list.
> @@ -2935,13 +2935,13 @@
> if (!RC->contains(Reg))
> return Error(RegLoc, "invalid register in register list");
> // List must be monotonically increasing.
> - if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) {
> + if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
> if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
> Warning(RegLoc, "register list not in ascending order");
> else
> return Error(RegLoc, "register list not in ascending order");
> }
> - if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
> + if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
> Warning(RegLoc, "duplicated register (" + RegTok.getString() +
> ") in register list");
> continue;
> @@ -5304,8 +5304,8 @@
> case ARM::LDRD_POST:
> case ARM::LDREXD: {
> // Rt2 must be Rt + 1.
> - unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
> - unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
> + unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
> + unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
> if (Rt2 != Rt + 1)
> return Error(Operands[3]->getStartLoc(),
> "destination operands must be sequential");
> @@ -5313,8 +5313,8 @@
> }
> case ARM::STRD: {
> // Rt2 must be Rt + 1.
> - unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
> - unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
> + unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
> + unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
> if (Rt2 != Rt + 1)
> return Error(Operands[3]->getStartLoc(),
> "source operands must be sequential");
> @@ -5324,8 +5324,8 @@
> case ARM::STRD_POST:
> case ARM::STREXD: {
> // Rt2 must be Rt + 1.
> - unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
> - unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
> + unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
> + unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
> if (Rt2 != Rt + 1)
> return Error(Operands[3]->getStartLoc(),
> "source operands must be sequential");
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=161628&r1=161627&r2=161628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h Thu Aug 9 17:10:21 2012
> @@ -161,82 +161,6 @@
> }
> } // namespace ARM_MB
>
> -/// getARMRegisterNumbering - Given the enum value for some register, e.g.
> -/// ARM::LR, return the number that it corresponds to (e.g. 14).
> -inline static unsigned getARMRegisterNumbering(unsigned Reg) {
> - using namespace ARM;
> - switch (Reg) {
> - default:
> - llvm_unreachable("Unknown ARM register!");
> - case R0: case S0: case D0: case Q0: return 0;
> - case R1: case S1: case D1: case Q1: return 1;
> - case R2: case S2: case D2: case Q2: return 2;
> - case R3: case S3: case D3: case Q3: return 3;
> - case R4: case S4: case D4: case Q4: return 4;
> - case R5: case S5: case D5: case Q5: return 5;
> - case R6: case S6: case D6: case Q6: return 6;
> - case R7: case S7: case D7: case Q7: return 7;
> - case R8: case S8: case D8: case Q8: return 8;
> - case R9: case S9: case D9: case Q9: return 9;
> - case R10: case S10: case D10: case Q10: return 10;
> - case R11: case S11: case D11: case Q11: return 11;
> - case R12: case S12: case D12: case Q12: return 12;
> - case SP: case S13: case D13: case Q13: return 13;
> - case LR: case S14: case D14: case Q14: return 14;
> - case PC: case S15: case D15: case Q15: return 15;
> -
> - case S16: case D16: return 16;
> - case S17: case D17: return 17;
> - case S18: case D18: return 18;
> - case S19: case D19: return 19;
> - case S20: case D20: return 20;
> - case S21: case D21: return 21;
> - case S22: case D22: return 22;
> - case S23: case D23: return 23;
> - case S24: case D24: return 24;
> - case S25: case D25: return 25;
> - case S26: case D26: return 26;
> - case S27: case D27: return 27;
> - case S28: case D28: return 28;
> - case S29: case D29: return 29;
> - case S30: case D30: return 30;
> - case S31: case D31: return 31;
> -
> - // Composite registers use the regnum of the first register in the list.
> - /* Q0 */ case D0_D2: return 0;
> - case D1_D2: case D1_D3: return 1;
> - /* Q1 */ case D2_D4: return 2;
> - case D3_D4: case D3_D5: return 3;
> - /* Q2 */ case D4_D6: return 4;
> - case D5_D6: case D5_D7: return 5;
> - /* Q3 */ case D6_D8: return 6;
> - case D7_D8: case D7_D9: return 7;
> - /* Q4 */ case D8_D10: return 8;
> - case D9_D10: case D9_D11: return 9;
> - /* Q5 */ case D10_D12: return 10;
> - case D11_D12: case D11_D13: return 11;
> - /* Q6 */ case D12_D14: return 12;
> - case D13_D14: case D13_D15: return 13;
> - /* Q7 */ case D14_D16: return 14;
> - case D15_D16: case D15_D17: return 15;
> - /* Q8 */ case D16_D18: return 16;
> - case D17_D18: case D17_D19: return 17;
> - /* Q9 */ case D18_D20: return 18;
> - case D19_D20: case D19_D21: return 19;
> - /* Q10 */ case D20_D22: return 20;
> - case D21_D22: case D21_D23: return 21;
> - /* Q11 */ case D22_D24: return 22;
> - case D23_D24: case D23_D25: return 23;
> - /* Q12 */ case D24_D26: return 24;
> - case D25_D26: case D25_D27: return 25;
> - /* Q13 */ case D26_D28: return 26;
> - case D27_D28: case D27_D29: return 27;
> - /* Q14 */ case D28_D30: return 28;
> - case D29_D30: case D29_D31: return 29;
> - /* Q15 */
> - }
> -}
> -
> /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
> ///
> static inline bool isARMLowRegister(unsigned Reg) {
>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=161628&r1=161627&r2=161628&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Thu Aug 9 17:10:21 2012
> @@ -18,6 +18,7 @@
> #include "MCTargetDesc/ARMMCExpr.h"
> #include "MCTargetDesc/ARMMCTargetDesc.h"
> #include "llvm/MC/MCCodeEmitter.h"
> +#include "llvm/MC/MCContext.h"
> #include "llvm/MC/MCExpr.h"
> #include "llvm/MC/MCInst.h"
> #include "llvm/MC/MCInstrInfo.h"
> @@ -38,11 +39,12 @@
> void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
> const MCInstrInfo &MCII;
> const MCSubtargetInfo &STI;
> + const MCContext &CTX;
>
> public:
> ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
> MCContext &ctx)
> - : MCII(mcii), STI(sti) {
> + : MCII(mcii), STI(sti), CTX(ctx) {
> }
>
> ~ARMMCCodeEmitter() {}
> @@ -405,7 +407,7 @@
> SmallVectorImpl<MCFixup> &Fixups) const {
> if (MO.isReg()) {
> unsigned Reg = MO.getReg();
> - unsigned RegNo = getARMRegisterNumbering(Reg);
> + unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
>
> // Q registers are encoded as 2x their register number.
> switch (Reg) {
> @@ -434,7 +436,7 @@
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
>
> - Reg = getARMRegisterNumbering(MO.getReg());
> + Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
>
> int32_t SImm = MO1.getImm();
> bool isAdd = true;
> @@ -709,8 +711,8 @@
> // {2-0} = Rn
> const MCOperand &MO1 = MI.getOperand(OpIdx);
> const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
> - unsigned Rn = getARMRegisterNumbering(MO1.getReg());
> - unsigned Rm = getARMRegisterNumbering(MO2.getReg());
> + unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> + unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
> return (Rm << 3) | Rn;
> }
>
> @@ -726,7 +728,7 @@
> // If The first operand isn't a register, we have a label reference.
> const MCOperand &MO = MI.getOperand(OpIdx);
> if (!MO.isReg()) {
> - Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
> + Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
> Imm12 = 0;
> isAdd = false ; // 'U' bit is set as part of the fixup.
>
> @@ -806,7 +808,7 @@
> // If The first operand isn't a register, we have a label reference.
> const MCOperand &MO = MI.getOperand(OpIdx);
> if (!MO.isReg()) {
> - Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
> + Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
> Imm8 = 0;
> isAdd = false ; // 'U' bit is set as part of the fixup.
>
> @@ -842,7 +844,7 @@
> // {7-0} = imm8
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
> - unsigned Reg = getARMRegisterNumbering(MO.getReg());
> + unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> unsigned Imm8 = MO1.getImm();
> return (Reg << 8) | Imm8;
> }
> @@ -925,8 +927,8 @@
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx+1);
> const MCOperand &MO2 = MI.getOperand(OpIdx+2);
> - unsigned Rn = getARMRegisterNumbering(MO.getReg());
> - unsigned Rm = getARMRegisterNumbering(MO1.getReg());
> + unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> + unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
> bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
> ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
> @@ -956,7 +958,7 @@
> // {12} isAdd
> // {11-0} imm12/Rm
> const MCOperand &MO = MI.getOperand(OpIdx);
> - unsigned Rn = getARMRegisterNumbering(MO.getReg());
> + unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
> Binary |= Rn << 14;
> return Binary;
> @@ -979,7 +981,7 @@
> ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
> Binary <<= 7; // Shift amount is bits [11:7]
> Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
> - Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
> + Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0]
> }
> return Binary | (isAdd << 12) | (isReg << 13);
> }
> @@ -992,7 +994,7 @@
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx+1);
> bool isAdd = MO1.getImm() != 0;
> - return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
> + return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4);
> }
>
> uint32_t ARMMCCodeEmitter::
> @@ -1010,7 +1012,7 @@
> uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
> // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
> if (!isImm)
> - Imm8 = getARMRegisterNumbering(MO.getReg());
> + Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> return Imm8 | (isAdd << 8) | (isImm << 9);
> }
>
> @@ -1028,7 +1030,7 @@
>
> // If The first operand isn't a register, we have a label reference.
> if (!MO.isReg()) {
> - unsigned Rn = getARMRegisterNumbering(ARM::PC); // Rn is PC.
> + unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
>
> assert(MO.isExpr() && "Unexpected machine operand type!");
> const MCExpr *Expr = MO.getExpr();
> @@ -1038,14 +1040,14 @@
> ++MCNumCPRelocations;
> return (Rn << 9) | (1 << 13);
> }
> - unsigned Rn = getARMRegisterNumbering(MO.getReg());
> + unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> unsigned Imm = MO2.getImm();
> bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
> bool isImm = MO1.getReg() == 0;
> uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
> // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
> if (!isImm)
> - Imm8 = getARMRegisterNumbering(MO1.getReg());
> + Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
> }
>
> @@ -1073,7 +1075,7 @@
> // {2-0} = Rn
> const MCOperand &MO = MI.getOperand(OpIdx);
> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
> - unsigned Rn = getARMRegisterNumbering(MO.getReg());
> + unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> unsigned Imm5 = MO1.getImm();
> return ((Imm5 & 0x1f) << 3) | Rn;
> }
> @@ -1100,7 +1102,7 @@
> // If The first operand isn't a register, we have a label reference.
> const MCOperand &MO = MI.getOperand(OpIdx);
> if (!MO.isReg()) {
> - Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
> + Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
> Imm8 = 0;
> isAdd = false; // 'U' bit is handled as part of the fixup.
>
> @@ -1146,7 +1148,7 @@
> ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
>
> // Encode Rm.
> - unsigned Binary = getARMRegisterNumbering(MO.getReg());
> + unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
>
> // Encode the shift opcode.
> unsigned SBits = 0;
> @@ -1171,7 +1173,7 @@
> // Encode the shift operation Rs.
> // Encode Rs bit[11:8].
> assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
> - return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
> + return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
> }
>
> unsigned ARMMCCodeEmitter::
> @@ -1190,7 +1192,7 @@
> ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
>
> // Encode Rm.
> - unsigned Binary = getARMRegisterNumbering(MO.getReg());
> + unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
>
> // Encode the shift opcode.
> unsigned SBits = 0;
> @@ -1229,9 +1231,9 @@
>
> // Encoded as [Rn, Rm, imm].
> // FIXME: Needs fixup support.
> - unsigned Value = getARMRegisterNumbering(MO1.getReg());
> + unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
> Value <<= 4;
> - Value |= getARMRegisterNumbering(MO2.getReg());
> + Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
> Value <<= 2;
> Value |= MO3.getImm();
>
> @@ -1245,7 +1247,7 @@
> const MCOperand &MO2 = MI.getOperand(OpNum+1);
>
> // FIXME: Needs fixup support.
> - unsigned Value = getARMRegisterNumbering(MO1.getReg());
> + unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
>
> // Even though the immediate is 8 bits long, we need 9 bits in order
> // to represent the (inverse of the) sign bit.
> @@ -1307,7 +1309,7 @@
> ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
>
> // Encode Rm.
> - unsigned Binary = getARMRegisterNumbering(MO.getReg());
> + unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
>
> // Encode the shift opcode.
> unsigned SBits = 0;
> @@ -1363,7 +1365,7 @@
>
> if (SPRRegs || DPRRegs) {
> // VLDM/VSTM
> - unsigned RegNo = getARMRegisterNumbering(Reg);
> + unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
> unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
> Binary |= (RegNo & 0x1f) << 8;
> if (SPRRegs)
> @@ -1372,7 +1374,7 @@
> Binary |= NumRegs * 2;
> } else {
> for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
> - unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
> + unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg());
> Binary |= 1 << RegNo;
> }
> }
> @@ -1388,7 +1390,7 @@
> const MCOperand &Reg = MI.getOperand(Op);
> const MCOperand &Imm = MI.getOperand(Op + 1);
>
> - unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
> + unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
> unsigned Align = 0;
>
> switch (Imm.getImm()) {
> @@ -1411,7 +1413,7 @@
> const MCOperand &Reg = MI.getOperand(Op);
> const MCOperand &Imm = MI.getOperand(Op + 1);
>
> - unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
> + unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
> unsigned Align = 0;
>
> switch (Imm.getImm()) {
> @@ -1437,7 +1439,7 @@
> const MCOperand &Reg = MI.getOperand(Op);
> const MCOperand &Imm = MI.getOperand(Op + 1);
>
> - unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
> + unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
> unsigned Align = 0;
>
> switch (Imm.getImm()) {
> @@ -1456,7 +1458,7 @@
> SmallVectorImpl<MCFixup> &Fixups) const {
> const MCOperand &MO = MI.getOperand(Op);
> if (MO.getReg() == 0) return 0x0D;
> - return getARMRegisterNumbering(MO.getReg());
> + return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
> }
>
> unsigned ARMMCCodeEmitter::
>
>
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