[llvm-commits] [llvm] r161377 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td test/MC/Mips/sext_64_32.ll

[Jack Carter]

Author: jacksprat
Date: Mon Aug  6 19:35:22 2012
New Revision: 161377

URL: http://llvm.org/viewvc/llvm-project?rev=161377&view=rev
Log:
The define for 64 bit sign extension neglected to 
initialize fields of the class that it used.

The result was nonsense code.

Before:
0000000000000000 <foo>:
   0:    00441100     0x441100
   4:    03e00008     jr    ra
   8:    00000000     nop

After:
0000000000000000 <foo>:
   0:    00041000     sll    v0,a0,0x0
   4:    03e00008     jr    ra
   8:    00000000     nop 

Added:
    llvm/trunk/test/MC/Mips/sext_64_32.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=161377&r1=161376&r2=161377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Aug  6 19:35:22 2012
@@ -219,13 +219,14 @@
 def DEXT : ExtBase<3, "dext", CPU64Regs>;
 def DINS : InsBase<7, "dins", CPU64Regs>;
 
-def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
-                   "dsll\t$rd, $rt, 32", [], IIAlu>;
-def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
-                  "sll\t$rd, $rt, 0", [], IIAlu>;
-let isCodeGenOnly = 1 in
-def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
-                  "sll\t$rd, $rt, 0", [], IIAlu>;
+let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
+  def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+                     "dsll\t$rd, $rt, 32", [], IIAlu>;
+  def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
+                    "sll\t$rd, $rt, 0", [], IIAlu>;
+  def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
+                    "sll\t$rd, $rt, 0", [], IIAlu>;
+}
 }
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions

Added: llvm/trunk/test/MC/Mips/sext_64_32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/sext_64_32.ll?rev=161377&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/sext_64_32.ll (added)
+++ llvm/trunk/test/MC/Mips/sext_64_32.ll Mon Aug  6 19:35:22 2012
@@ -0,0 +1,15 @@
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+
+; Sign extend from 32 to 64 was creating nonsense opcodes
+
+; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0
+
+; ModuleID = '../sext.c'
+;target datalayout = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v64:64:64-n32"
+;target triple = "mips64el-unknown-linux"
+
+define i64 @foo(i32 %ival) nounwind readnone {
+entry:
+  %conv = sext i32 %ival to i64
+  ret i64 %conv
+}