[llvm-commits] [llvm] r161299 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll

[Jakob Stoklund Olesen]

On Aug 4, 2012, at 6:16 AM, Anton Korobeynikov <asl at math.spbu.ru> wrote:

> Author: asl
> Date: Sat Aug  4 08:16:12 2012
> New Revision: 161299
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=161299&view=rev
> Log:
> Add stack spill / reload instructions for DTriple and DQuad register classes, which
> were missed for no reason. This fixes PR13377

Thanks!

> +        // Use aligned spills if the stack can be realigned.
> +        if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
> +          AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
> +                     .addFrameIndex(FI).addImm(16)
> +                     .addReg(SrcReg, getKillRegState(isKill))
> +                     .addMemOperand(MMO));

I believe the 3-register vld1 instruction only supports 8-byte alignment.

> 
> --- llvm/trunk/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll Sat Aug  4 08:16:12 2012

You can probably reduce this to a single basic block by adding an inline asm that clobbers the callee saved d registers.

/jakob