[llvm-commits] [PATCH 2/6] revise/enhance atomic primitive code generation

[Michael Liao]

Hi

Here's the 2nd patch from a series of patch revising/enhancing the
current atomic primitive code generation support in X86 backend. This
patch revises all pseudo atomic instruction based on CMPXCHG.

* One load is removed from the spin-loop to reduce loop overhead as
CMPXCHG will load that memory operand.
* Since most of them shares the same code skelteton and only differ each
other by the updating logic, they are unified into the same one,
EmitAtomicLoadArith and EmitAtomicLoadArith6432 (for 64-bit operand on
32-bit target.)
* remove physical register constraints on pseudo atomic instructions
* add pseudo CMOV support if the underly targets have no CMOV feature
* refine test cases due to the spin-loop change

Please review them and commit if they're OK.

Yours
- Michael
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