[llvm-commits] [PATCH] revise/enhance atomic primitive code generation

[Michael Liao]

Hi Folks

Before I submit the patch adding TSX [1][2] support for X86 backend, I
want first contribute back the effort revising/enhancing the current X86
backend for atomic primitive code generation. I made the following
changes

- unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArith and
  merge them together
- refine spin-loop to reduce one unnecessary load
- add missing i8 max/min/umax/umin
- add missing i64 max/min/umax/umin on 32-bit target
- refine atomic instruction td files to use the template for groups of
  instructions
- Output 'lock' prefix in assembler printer to simplify the assembly
  text in td files

Please review the attached patch and commit if it's OK.

Yours
- Michael

---
[1] http://software.intel.com/file/36945
[2]
http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/
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