[llvm-commits] [PATCH] Fix PR11334

[Rotem, Nadav]

Hi Michael, 

In your patch you are counting on the type-legalizer to scalarize the FPEXT operation, only to gether it again. I think that the pre-type-legalization DAGCombine code would be short and simple.  Why not implement a DAGCombine optimization which works on vector FPEXT ISDs ?  I understand that it will be more difficult to handle types such as <3 x float>, but are these really important ?   

Thanks,
Nadav

-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Michael Liao
Sent: Wednesday, July 25, 2012 00:28
To: llvm-commits at cs.uiuc.edu
Subject: [llvm-commits] [PATCH] Fix PR11334

Hi

Please review the attached patch fixing PR11334. With this patch, the test case in PR11334 could generate the expected insn, CVTPS2PD instead of series of CVTSS2SD. An enhanced test case is included as well.

Yours
- Michael
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