[llvm-commits] [PATCH] Fix assembly of narrow Thumb data processing instructions

[Richard Barton]

Hello Reviewers

The attached patch implements correct assembly of Thumb dp-operations with both
three and two register syntaxes.

i.e. AND, EOR, LSL, LSR, ASR, ADC, SBC, ROR, and ORR.

The assembly syntax for these instructions is of the form:

AND{S}{<c>}{<q>}  {<Rd>,} <Rn>, <Rm> {, <shift>}

The optional Rd argument allows the use of the short encoding when Rd == Rn (and
other conditions hold.) The assembler should always prefer the short encoding
over the wide in these cases, unless the wide encoding is specifically requested
with '.W'.

In addition, ADD, EOR, ADC and ORR are commutative, so the narrow encoding is
also available when Rd == Rm (as well as the other conditions holding.)

The additional conditions are:
 - Rd, Rn and Rm are all in the range R0 - R7.
 - The instruction is flag-setting and not in an IT block, or not-flag setting
and in an IT block.
 - No shift is applied to the instruction.

The attached patch uses the validateInstruction callback to chose the narrow
encodings in the correct circumstances, and adds a new regression test.

Please review.

Regards,
Richard Barton
ARM Ltd, Cambridge

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